JPH0744448A - Memory access device - Google Patents

Abstract

PURPOSE:To attain a stable high speed by implementing read/write alternately while dividing one instruction implementation cycle into two stages to avoid simultaneously read/write. CONSTITUTION:Delay circuits 7, 8 generate a fetch stage signal and an implementation stage signal based on a clock of a 1/2 instruction implementation cycle, the implementation instruction cycle is bisected as the fetch stage and the implementation stage, and a fetch register 11, a micro instruction register 12, a write address register 13, a read data buffer 16 and a write data buffer 17 are formed to implement reading in the fetch stage, implementation of the instruction in the succeeding implementation stage, write data address generation and writing in the succeeding implementation stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to speeding up memory access of an information processing device. In recent years, as information processing apparatuses have become faster, faster memory access has been demanded. With downsizing, it is particularly required to speed up memory access without using an expensive high-speed storage element. ing.

[0002]

2. Description of the Related Art FIG. 16 is a principle block diagram of a conventional example, and is a diagram of a memory access portion generally used in an information processing apparatus. FIG. 17 is an operation time chart of the memory access part. The control storage 9 stores instructions executed by the information processing device.

An instruction from the control storage 9 is set in the fetch register 31 at the timing of the fetch clock. The contents of the fetch register 31 are set in the micro instruction register 32 at the timing of the execution clock. The fetch clock and the execution clock alternate, and the interval between the execution clock and the next execution clock is called one instruction execution cycle. In a normal instruction, the memory is read or written during one instruction execution cycle.

[0004]

The following problems occur when attempting to speed up such memory access.
If a storage element with a large read access time and a large write data setup is used, the delay is large and there is a limit to the speedup. If a high-speed storage element is used for this solution, the cost will increase.

In the data transfer in the memory, it is necessary to read and write at the same time within one instruction execution cycle, and only a limited type of memory satisfying this requirement can be used. In order to realize the partial write, it is necessary to take a measure to use a storage element having a write enable for each part or divide the memory by the data width of the partial write, which increases the cost.

Since two clocks are used, the skew between the clocks cannot be ignored during high speed operation,
It is difficult to speed up. An object of the present invention is to solve the above problems and realize and provide a memory that can be accessed at high speed even when an inexpensive storage element having a relatively long access time is used.

[0007]

[Means for Solving the Problems]

[First to Third Inventions] FIG. 1 is a block diagram showing the principle of the present invention. FIG. 5 is an operation time chart when one instruction is executed according to the present invention. FIG. 6 is an operation time chart during continuous execution of instructions of the present invention.

FIG. 7 is a time chart during the read operation. FIG. 8 is a time chart during the write operation. In order to avoid simultaneous reading and writing within one instruction execution cycle, which is a factor that hinders speedup, a fetch stage signal synchronized with the fetch clock based on the clock and a 1/2 instruction execution cycle delay with respect to the fetch stage signal The clock stage unit 10 for generating the execution stage signal is provided,
A fetch register 11 is provided to set and store an instruction fetched from the control storage 9 in which an instruction to be executed in the information processing device is stored, and the contents of the fetch register 11 are set in the execution stage. And a microinstruction register 12 for storing
The write data address having the content of 2 is set in the execution stage, and the write address register 13 for storing one instruction execution cycle is provided.
An address multiplexer 14 that alternately switches the read address stored in 1 and the write address stored in the write address register 12 to the memory by alternately switching every 1/2 instruction execution cycle between the fetch stage and the execution stage. Provided is a read data buffer 16 for setting read data in the execution stage and storing one instruction execution cycle, and providing a write data buffer 17 for setting write data in the execution stage and storing one instruction execution cycle, and executing the instruction Divide the cycle into a read cycle in the latter half and a write cycle in the first half,
Data is read from the memory 15 in the second half read cycle, and data is written to the memory 15 in the first half write cycle of the next instruction execution cycle.

Further, the read data address is set in the fetch register 11 at the fetch stage so that the read data for instruction execution is fetched just before the instruction execution cycle for executing the instruction, and the address multiplexer 1
Each register is configured to access and read data through 4 and set and execute an instruction in the micro instruction register 12 in the subsequent execution stage.

Further, an instruction is set and executed in the micro instruction register 12 at the execution stage so that the write data executed by the instruction is written immediately after the instruction execution cycle for executing the instruction, and the write address register is executed at the subsequent clock. The write data address is set in 13, and each register is configured to access and write data through the address multiplexer 14.

[Claim 4] FIG. 2 is a principle block diagram of claim 4. FIG. 6 is a time chart during the bypass operation. In order to avoid a data contradiction in which old data is read when the read address and the write address match, a match signal is output when the read data address and the write data address match. A match determination section 18 is provided, and a read data multiplexer 19 that selects either write data or read data from the memory and outputs the read data to the read data buffer 16 is provided with the match signal from the match determination section 18 as a control signal. When the read data address and the write data address match, the read data multiplexer 19 bypasses and connects the write data to the read data buffer 16 so that the immediately preceding write data is used as the read data.

[Claim 5] FIG. 3 is a principle block diagram of claim 5. FIG. 10 is a flowchart for the partial write operation. In order to enable partial writing of data, the data to be handled is divided into upper data and lower data, and the upper data and the read of the write data to the write data buffer 17 are read. 2 with the upper data of the read data from the data buffer 16
And an upper write data multiplexer that outputs the upper data of the write data to the write data buffer 17 only when the upper write data set signal is on, and the lower data of the write data to the write data buffer 17 and the read data buffer. And a lower write data multiplexer which outputs lower data of the read data from the write data buffer 17 to the write data buffer 17 only when the lower write data set signal is ON. The upper data or the lower data is written by controlling the write data set signal and the lower write data set signal.

[Claim 6] FIG. 4 is a principle block diagram of claim 6. In order to avoid clock skew in the configurations of claims 1 to 5, a delay circuit 7 for one clock is used.
Means for generating a fetch stage signal whose cycle is one instruction execution cycle and which lasts ½ instruction execution cycle, and a 1-clock delay circuit 8 to which the fetch stage signal is input is used as a basic clock. Control is performed to control the fetch stage signal to 1 in the instruction execution cycle.
A means for generating an execution stage signal delayed by 1/2 is provided, and 1
The instruction execution cycle is divided into two stages, that is, a fetch stage and an execution stage, each of which is ½ of the instruction execution cycle, and each unit is controlled by one clock in each stage.

[0014]

The following effects can be obtained by the memory access device of the present invention having such a configuration. [Claim 1] FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 5 is a time chart when one instruction is executed according to the present invention. FIG. 6 is an operation time chart during continuous execution of instructions of the present invention. Regarding the read data, at the same time when the instruction is set in the fetch register 11, the memory read address of the fetch register 11 becomes a memory address through the address multiplexer 14, the memory read is performed, and the read data is stored in the read data buffer 16 in the subsequent execution stage. Is set.

Regarding write data, the write data generated in the instruction execution cycle is set in the write data buffer 17 in the subsequent execution stage, and at the same time, the write data address of the micro instruction register 12 is set in the write address register 13. At the clock of the next instruction execution cycle, the content of the write address register 13 becomes the memory write address through the address multiplexer 14, and the write data in the write data buffer 17 is written in the memory 15.

As shown in FIG. 6, the first half of the instruction execution cycle is divided into the write operation and the second half is divided into the read operation, and the read operation and the write operation are not performed at the same time. [Claim 2] FIG. 7 is a time chart during a read operation. The fetched instruction is set in the fetch register 11 in the fetch stage, and the read memory address of the set instruction becomes the memory address when the synchronization signal immediately before the instruction execution cycle is turned off, and the memory read is performed. Read data is read data buffer 1
Set to 6.

In this way, the read operation is performed immediately before the instruction is executed. [Claim 3] FIG. 8 is a time chart of a write operation. The fetched instruction is set in the fetch register 11 in the fetch stage, and set in the micro instruction register 12 in the subsequent execution stage.

The register write address of the instruction stored in the micro instruction register 12 is set in the write address register 13 in the next fetch stage, and the write memory address is reached at the time when the synchronization signal at the beginning of the next instruction execution cycle is turned on. Then, the write data of the write data buffer 17 is written at this address. In this way, the write operation is performed at the beginning of the next instruction execution cycle immediately after the instruction is executed.

[Claim 4] FIG. 2 is a principle block diagram of claim 4. FIG. 8 is a time chart during the bypass operation. When a match signal is output from the match determination unit 18 provided for detecting the match between the write register address and the read register address, the read data multiplexer connects the write data output to the read data buffer 16.

By this bypass operation, it is possible to avoid the contradiction that the old data is read at the time of the instruction to read the data of the read register address which is the same as the write register address, and it is possible to read the intended correct data. [Claim 5] FIG. 3 is a principle block diagram of claim 5.

FIG. 10 is a time chart during the partial write operation. The write data multiplexer is divided into an upper data write data multiplexer 20 and a lower write data multiplexer 21. If the upper write data multiplexer 20 and the lower write data multiplexer 21 are controlled so that the upper write data multiplexer 20 selects and outputs the write data, and the lower write data multiplexer 21 selects and outputs the data of the read data buffer 16. The write data is written in the upper data, but the read data is written in the lower data, which is the same as before the execution.

The upper write data multiplexer 20 and the lower write data multiplexer 21 are selected so that the lower write data multiplexer 21 selects and outputs the write data, and the upper write data multiplexer 20 selects and outputs the data of the read data buffer 16. If controlled, the write data is written in the lower data, but the read data is written in the upper data, which is the same as before the execution.

As described above, by controlling the write data multiplexer, the upper data or the lower data can be partially written. [Claim 6] FIG. 4 is a principle block diagram of claim 6.
FIG. 15 is an operation time chart of the stage signal.

As shown in the operation time chart of FIG. 15, one instruction execution cycle is divided into two stages by a fetch stage signal and an execution stage signal which are created based on a clock having a half cycle of the instruction execution cycle. The control of each unit is performed by one clock in the fetch stage or the execution stage.

As a result, clock skew can be avoided even if the clock speed is increased, and the speed of the device can be increased.

[0027]

【Example】

[Claims 1-3] FIG. 11 is a block diagram of an embodiment of the present invention. Generation of the stage signal is performed as follows. Figure 1
5 is an operation time chart of the stage signal.

In the clock stage section, a fetch stage signal and an execution stage signal are created based on a clock and a synchronizing signal of 1/2 cycle of the instruction execution cycle. When the D-flip-flop 107 receives the synchronization signal and its output is off and the fetch inhibition signal is off, the next connected D
—The flip-flop 108 is triggered by the clock and the fetch stage signal is turned on.

The fetch inhibit signal is an external signal which is turned on when it is necessary to extend the instruction execution cycle.
Fetch stage signal is clock triggered D-
The flip-flop 108 receives it to generate an execution stage signal. Therefore, the execution stage signal becomes a signal delayed by one clock, that is, the 1/2 instruction cycle fetch stage signal.

Address generation and read / write operations are performed as follows. When the fetch stage signal is on and the fetch stage signal set signal is on, the instruction stored in the control storage 109 is set in the fetch register 111. As another method of setting an instruction in the fetch register, there is also a method of controlling only the clock of the fetch register 111 as shown in FIG. 14 and switching the input by the multiplexer 141, and the method is not limited.

The address portion of the set instruction is sent to the address multiplexer 114 as a read data address. The contents of the fetch register 111 are set in the micro instruction register 112 when the execution stage signal is on and the micro instruction register set signal is on.
At the same time, the execution of instructions is started.

The write address register 113 is a register that holds the address portion of the micro instruction register 112 and is set at each clock. The output of the write address register 113 is sent to the address multiplexer 114. The address multiplexer 114 selects the write data address of the write address register 113 when the fetch stage signal is on, and the write operation is performed. When the fetch stage signal is off, the read data address of the fetch register 111 is selected and the read operation is performed. In the memory address generation, the read operation and the write operation, one instruction execution cycle is divided into two stages, and the write operation and the read operation are performed in each stage, and the read and write operations are performed simultaneously. I will not be told.

The relationship between the read / write operation and instruction execution is as follows. When the fetch stage signal is on, the fetch register set signal is on, and the clock is on, the read data address is established, and when the execution stage signal is on, the data is read through the address multiplexer 114. When the micro instruction register 112 is on, the execution stage is on, and the next clock is turned on, the contents of the fetch register 111 are set in the micro instruction register 112 and the instruction is executed. The write data address portion of the micro instruction is set in the write address register 113 at the next clock, the write data address is established, the fetch stage signal is turned on, and the data write is performed through the address multiplexer 114.

In this way, the read operation is performed immediately before the instruction execution, and the write operation is performed immediately after the instruction execution. [Claim 4] FIG. 12 is a block diagram of an embodiment of claim 4.
When the read address and the write address match, the match determination unit 118 that detects the match compares the read data address and the write data address, and when they match, turns on the match signal and sends it to the read data multiplexer 119.

When the match signal is on and the write data set signal is on, the read data multiplexer 119 outputs 2
Write data is selected from the two inputs and bypassed and set in the read data buffer 116. In this way, it is possible to avoid a data contradiction in which old data that has not yet been written is read.

When the read address and the write address are not the same, the match signal is off and the read data multiplexer 119 sets the memory read data of the two inputs in the read data buffer 116. [Claim 5] FIG. 13 is a block diagram of an embodiment of claim 5.

The partial write instruction includes an instruction to write only the upper write data and an instruction to write only the lower write data. In the write command of only upper data,
When the upper write data set signal is turned on and the execution stage signal is turned on, the upper write data multiplexer 120 selects the upper write data as input data and sets it in the write data buffer 117. At this time, the lower write data set signal is turned off, the lower write data multiplexer 121 selects the output of the read data buffer 116, and the write data buffer 117.
However, the same data as the previous data will be set, and the lower data will not be changed.
The data in the write data buffer 117 is written in the memory 115 at the next clock. In this way, partial writing of only upper write data can be performed.

In the write instruction of only lower data,
When the lower write data set signal is turned on and the execution stage signal is turned on, the lower write data multiplexer 121 selects the lower write data as input data and sets it in the write data buffer 117. At this time, the upper write data set signal is turned off, the upper write data multiplexer 120 selects the output of the read data buffer 116, and the write data buffer 117.
However, the same data as the previous data will be set. In this way, partial writing of only lower write data can be performed.

[0039]

As described above, the instruction execution cycle is divided into the read cycle and the write cycle, the simultaneous access to the memory is avoided, the read is performed immediately before the instruction is executed, and the write is performed immediately after the instruction is executed. Error-free speedup can be achieved even with a slow memory.

The data inconsistency of reading the data before rewriting due to the read instruction immediately after the writing can be avoided by the data bypass control. In partial write, write data is aligned and written outside the memory, so the memory may use the same type as the total data width of the register. Also, it is not necessary to use a memory with write enable for each part.

Since the execution clock and the fetch clock are stage-controlled by one clock, the clock skew can be reduced and the speed can be stably increased.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram of the principle of claim 4.

FIG. 3 is a block diagram of the principle of claim 5.

FIG. 4 is a block diagram of the principle of claim 6.

FIG. 5 is an operation time chart of the present invention (when one instruction is executed)

FIG. 6 is an operation time chart of the present invention (at the time of continuous instruction execution)

FIG. 7 is a time chart during a read operation

FIG. 8 is a time chart during a write operation

FIG. 9 is a time chart during bypass operation.

FIG. 10 is a time chart during a partial write operation

FIG. 11 is a configuration diagram of an embodiment of the present invention.

FIG. 12 is a configuration diagram of an embodiment of claim 4;

FIG. 13 is a configuration diagram of an embodiment of claim 5;

FIG. 14 is another embodiment of the fetch register set.

FIG. 15 is an operation time chart of a stage signal

FIG. 16 is a principle block diagram of a conventional example.

FIG. 17 is an operation time chart of a conventional example.

[Explanation of symbols]

 7, 8: Delay circuit 9: Control storage 10: Clock stage unit 11: Fetch register 12: Micro instruction register 13: Write address register 14: Address multiplexer 15: Memory 16: Read data buffer 17: Write data buffer 18: Match determination Part 19: Read data multiplexer 20: Upper write data multiplexer 21: Lower write data multiplexer 31: Fetch register of conventional example 32: Micro instruction register of conventional example 34: Address register of conventional example

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[Procedure amendment]

[Submission date] December 10, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1] ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 24, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 12

[Correction method] Change

[Correction content]

[Fig. 12]

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Yamaguchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yasutoshi Sakurai 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takumi Nonaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kenji Hoshi, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor, Eiji Kanaya Kanagawa Prefecture 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Fujitsu Limited

Claims (6)

[Claims] 1. A delay circuit (7) for inputting a synchronizing signal and outputting a fetch stage signal synchronized with a fetch clock, based on a clock having a cycle half of an instruction execution cycle, and the delay circuit (7). ) As an input, and a delay circuit (8) that produces an execution stage signal that is delayed by 1/2 instruction execution cycle with respect to the fetch stage signal, and a clock stage section (10) A fetch register (11) that sets and stores the instruction fetched from the control storage (9) that stores the instruction to be stored, and sets and stores the contents of the fetch register (11) at the execution stage The micro instruction register (12) to be stored, and the micro instruction register (1
Write address register (13) that sets the write data address of 2) and stores it in one instruction execution cycle
And a read data address stored in the fetch register (11) and the write address register (13)
An address multiplexer (14) for alternately switching the write data address stored in the memory for every 1/2 instruction execution cycle, and outputting the read data address in the fetch stage and the write data address in the execution stage to the memory. A read data buffer (16) for setting read data in the execution stage to store one instruction execution cycle, and a write data buffer (17) for setting write data in the execution stage to store one instruction execution cycle And a memory access device. 2. The memory access device according to claim 1, wherein the fetch register (1
1) The data of the read data address pointed to by 1) is read through the address multiplexer (14), and the instruction of the content of the fetch register (11) is set in the micro instruction register (12) and executed in the subsequent execution stage. A memory access device characterized by being configured. 3. The memory access device according to claim 1, wherein the micro instruction register (1
The instruction set in 2) is executed, the write data address of the micro instruction register (12) is set in the write address register (13) at the next clock, and the write address register (1) is set in the subsequent execution stage.
A memory access device characterized in that the data of the write data address indicated by 3) is written through the address multiplexer (14). 4. The memory access device according to claim 1, further comprising: a match determining section (18) for outputting a match signal when two inputs of the read data address and the write data address match, and the match determining section. A read data multiplexer (19) for selecting two inputs of read data and write data by controlling with a match signal from (18) and outputting to a read data buffer is provided. The memory access device is characterized in that the read data multiplexer (19) bypasses the write data to the read data buffer and outputs the read data when the data is output. 5. The memory access device according to any one of claims 1 to 4, wherein two inputs of upper data of data to be written in a memory and upper data of the read data buffer (16) are selected to select the write data buffer ( 17) An upper write data multiplexer (20) for outputting to the upper part of
And a lower write data multiplexer (21) for selecting two inputs of the lower data of the data to be written in the memory and the lower data of the read data buffer (16) and outputting them to the lower portion of the write data buffer (17). )
And selecting the upper data of the data to be written to the memory when the upper write data set signal is applied to the upper write data multiplexer (20), and the lower write data multiplexer outputs the lower write data set signal to the lower write data multiplexer (21). The memory access device is characterized in that it is configured to select and output lower-order data of the tree data to be written to the memory when is added. 6. The memory access device according to claim 1, wherein a delay circuit (7) having a synchronizing signal as an input and a fetch stage signal as an output, and an output of the delay circuit (7) as an input, A memory access device characterized in that both the delay circuit (8) for outputting an execution stage signal and the delay circuit (8) are controlled by a clock having the same 1/2 instruction execution cycle period.