JPH04152426A - Elastic store memory control circuit - Google Patents

Abstract

PURPOSE:To secure the operation of a data speed converter circuit with a single elastic stores ES memory by performing the switch between a case where the input information is directly inputted to the ES memory and a case where the input information is inputted to the ES memory via a data shift circuit. CONSTITUTION:A dangerous area deciding circuit 24 checks whether a write address (c) is included in a dangerous area or not when an ES memory control start signal (a) is inputted. If the write timing is included in the dangerous area, a decision output (f) turns on the NAND circuits 31 and 35. Then the output of a 50-bit shift register 11 is selected and written in an ES memory 4 via a NAND circuit 33 as a signal (h). At the same time, the read timing shifted by 50 bits by the read timing 50-bit shift data is selected by the circuit 35 and inputted to the memory 4 via a NAND circuit 36. Thus the phase of the write address is shifted in order to prevent the outrunning.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to simplify processing when a read address and a write address are in a prohibited area and to reduce the circuit scale regarding an elastane ink store memory control circuit, and to reduce the circuit size. A shift circuit that provides a shift amount greater than the area, a control circuit that inputs the write timing and read timing of the elastic store memory, and detects that the phase difference between the write timing and read timing is within the prohibited area, and the input information. and a selector that inputs input information with a delay longer than the prohibited area and selects and outputs one input information based on the detection output from the control circuit, and an elastic that sequentially writes the output of the selector and reads the information according to the read timing. An elastic store memory control circuit including a store memory.

[Industrial Application Field] The present invention relates to an elastic store memory control circuit, and particularly to control of an elastic store memory related to data rate conversion of a digital transmission device.

When performing data rate conversion using elastic store memory, the read address may overtake the write address due to the proximity of the write address and the read address. If such overtaking occurs, the information stored in the memory will be destroyed and incorrect information will be output, so it is necessary to prevent such overtaking from occurring.

[Conventional technology]

A conventional data rate conversion control method will be explained using FIGS. 5 and 6.

Here, a case where the clock speed of the read address is faster than that of the write address will be explained.

First, input information is input to the first elastane ink store memory 5 (
(hereinafter referred to as ES memory).

In parallel with this, the control circuit 7 detects whether the write timing and read timing of the ES memory 5 are close to each other and are in a prohibited area (a range where the read address overtakes the write address) as shown in FIG. will be carried out. When the control circuit 7 detects that both timings are within the prohibited area, the ES memory to be written is switched from the first ES memory 5 to the second ES memory so as not to overtake the input information. Control is performed by a control circuit 7, and speed conversion of input information is performed using a double buffer format in which information written in the ES memory 5.6 is sequentially switched and outputted by a selector 8.

(Problems to be Solved by the Invention) In the conventional data rate conversion processing circuit as described above, in order to compensate for overtaking of data, input information is stored in a plurality of buffers in order to avoid overtaking of addresses.
Switching S memory.

For this reason, in the conventional data speed conversion circuit, the E for speed conversion is
Two S memories are required, which not only increases the number of signal lines, but also increases the circuit scale because the ES memory section, which is difficult to integrate into an LSI, is large.

Therefore, an object of the present invention is to simplify the processing when the above-mentioned read address and write address are within the prohibited area, and to reduce the circuit scale.

[Means to solve the problem] FIG. 1 shows a diagram of the principle of the present invention.

In the figure, first, a data shift circuit 1 applies a shift amount greater than the prohibited area to input information. In parallel with this, the write timing and read timing of the ES memory 4 are input to the control circuit 2, and it is determined whether or not both addresses are within the prohibited area.

Next, the selector 3 outputs switching information between the input information and the input information via the data shift circuit (2) to the ES memory 4 based on the determination result of the control circuit 2.

In the ES memory 4, information is written using a write clock whose phase has been corrected based on the determination result of the control circuit 2.

[Effect]

By comparing the write timing and read timing of the ES memory, determining whether the input information is within the prohibited area, and switching between inputting the input information directly to the ES memory or manually inputting it to the ES memory via the data shift circuit, A single ES memory can now operate as a data rate conversion circuit.

〔Example] A detailed explanation will be given below based on an example shown in the open view.

In the figure, data shift circuit 1 in FIG. 1 is replaced by 5 in FIG.
Corresponding to the 0-bit shift register 11, the control circuit 2 in FIG.
The selector 3 in FIG.
are the NAND circuits 31 to 36 and the inverter 37 in FIG.
It corresponds to the part consisting of.

The present invention will be described in detail below with reference to FIGS. 2 to 4.

First, as a stage before starting up the circuit, the input information shown in Figure 3 (b
) is input to the 50-bit shift register 11, and the ES memory write timing (FIG. 3(C)) and read timing (FIG. 3(d)) are input to the control circuit 2.

In the control circuit 2, the write timing is input to the dangerous area determination circuit 24, and the read timing is input to the synchronous counter 21.
is input. The synchronization counter 21 sequentially counts input read timings and outputs them to the dangerous area decoder 22 and 50 focus shift decoder 23. here,
The dangerous area decoder outputs a dangerous area signal indicating a dangerous area (an area where overtaking occurs) based on the manually inputted readout timing. This dangerous area will be explained with reference to FIG. 4. It shows the minimum range in which write addresses and read addresses do not overtake.

This dangerous area signal is input to the dangerous area determination circuit 24.

In the above state, the elastic store memory control start signal shown in FIG. 3(a) is input.

Here, first, the dangerous area determination circuit 24 detects whether the write address (C) is within the dangerous area.

If the write address does not exist in the dangerous area as a result of this detection, the dangerous area judgment output () is the NAN via the inverter.
The D circuit 32 and the NAND circuit 34 are turned on, and the input information (b) is written into the ES memory 4 via the NAND circuit 33. In addition, the read timing (cl) as it is input is input to the NAND circuit 34 and the NAND
The signal is input to the ES memory 4 via the circuit 36.

Next, in the dangerous area judgment circuit 24, if the write timing exists within the dangerous area, the dangerous area judgment output (f) is N.
The inputs of the AND circuits 31 and 35 are turned ON, and the output of the 50-bit shift register is selected and written into the ES memory 4 via the NAND circuit 33 in the form shown in FIG. 4(5). In addition, the read timing is 50 bits with a 50-bint shift data.
The read timing shifted by 0 bits is selected by the NAND circuit 35 and inputted to the ES memory 4 via the NAND circuit 36.

In this way, the phase shift of the write address as shown by the dotted line in FIG. 4 is performed to prevent overtaking.

〔Effect of the invention〕

As described above, in the present invention, one elastic store memory is used, and troubles such as address overtaking can be easily avoided, and since only one elastic store memory is used, which cannot be implemented on an LSI, it is easy to implement on an LSI. It became possible to create a suitable circuit configuration.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is an embodiment of the present invention, Figure 3 is a diagram showing each signal of Figure 1 of the present invention, and Figure 4 is address overtaking avoidance of the present invention. An explanatory diagram of means. Figure 5 is a conventional elastic store memory control street, Part 6 is an explanatory diagram of address overtaking, 1...Data shift circuit, 2...Control circuit 3...Selector 4...Elastic ink store memory

Claims (1)

[Claims] A data rate conversion circuit using an elastic store memory that writes and reads information in parallel, comprising: a shift circuit (1) that shifts input information by an amount greater than a prohibited area; and an elastic store memory. (4) A control circuit (2) that inputs the write timing and read timing and detects that the phase difference between the write timing and read timing is within the prohibited area, and a control circuit (2) that provides the input information and a delay exceeding the prohibited area. Enter the input information and control circuit (2)
It is characterized by comprising a selector (3) that selects and outputs one input information based on a detection output from the selector (3), and an elastic store memory (4) that sequentially writes the output of the selector (3) and reads out the information according to the read timing. Elastic store memory control circuit.