JPS63283361A - Parallel picture signal output circuit - Google Patents

Abstract

PURPOSE:To simply control a parallel picture signal by using a line memory (FIFO) and providing a refresh function by a selector. CONSTITUTION:The selector 10 selects a next line signal string inputted from a picture signal reading part and the input of a current line FIFO 30 from the current line signal string of the output of the current line FIFO 30 and a selector 20 selects the input of a preceding line FIFO 40 from the preceding line signal string of the output of the current line signal string and the preceding line FIFO 40. Namely, the current line FIFO 30 inputs the next line signal string and outputs the current line signal string before one line, the preceding line FIFO 40 inputs the current line signal string and outputs the preceding lie signal string before one line. In such a way, a picture signal of three lines is outputted in parallel. Then, the refresh is carried out by using a block in which an output picture signal string is considered to be invalidated and the respective internal data of the respective FIFOs 30, 40 is refreshed. Thereby, the parallel signal can be simply controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing circuit for a facsimile machine, etc., and particularly to a circuit having processing using a delay line.

2. Description of the Related Art A parallel image signal output circuit in a conventional one-temperature signal processing section has a configuration as shown in FIG. In FIG. 2, reference numbers 10' and 20' represent three-state buffers.

30' and 40' indicate keys, and 50, 60, and 70 indicate registers, respectively.

The multilevel image signal sequence input from the image signal reading section is as follows.

It is output as the next line signal train, and when CLKO becomes "0", it is written into the current line RAM 30' via the first stage 3-state buffer 10'. At the same time, the current line signal train that had been stored in the current line RAM 30' is transferred to the previous line RAM 30' via the second stage 3-state buffer 20'.
will be written to. When eLK O becomes "1", RAM
At the same time as the output of the address counter 80 is incremented, the data output of the current line RAM 30' is output as the current line signal string, and the data output of the previous line RAM 40' is output as the previous line as an odd column.

Finally, each signal sequence of the previous line, current line, and next line is C
It is synchronized by LK1 and output.

Problems to be Solved by the Invention In the interface with Makoto in the conventional parallel signal output circuit described above, a clock with the same frequency as the data and a clock delayed by buffer 7, etc. are used to read and write within one clock. It is carried out. This is very different from the general method of using a clock with twice the frequency of data and switching between read and write every clock.

However, although this conventional method using parallel signal output circuits does not require the use of a clock with twice the frequency of the data, it complicates the 4-circuit design and has the disadvantage that high reliability cannot be expected. be.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel parallel image signal output circuit which makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the picture No. 1 parallel circuit according to the present invention has two FIFOs corresponding to the odd row and previous line picture signal train and a single picture signal for the current line picture. A selector that selects the input of the current line FIFO from the next line signal string input from the reading section and the current line signal string that is the output of the current line FIFO, and the previous line signal that is the output of the current line signal string and the previous line FIFO. It is comprised of a selector that selects the input of the previous line FIFO from a column, and three registers corresponding to the odd columns of the next line, current line, and previous line, respectively.

EXAMPLE Next, a preferred example of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one practical example of the present invention.

In FIG. 1, reference numbers 10 and 20 are selectors.

30, 40 indicates PIFo, and 50, 60, and 70 indicate registers, respectively.

Each of the selectors 10 and 20 is switched by a signal SENB representing the valid section of the one temperature code series. Signal 8 E
When NB becomes @O”, line start pulse FFRN
The address of each PIFO 30, 40 is reset, and from the rising edge of the next clock until the signal 8ENB becomes ``1'', while inputting the next line signal train to the current line FIFO 30ti, the current line signal of the previous line is input. Output columns. The previous line PIFO 40 receives the current line signal string and outputs the previous line signal string one line before the current line signal string. In this way, image signals for three lines are output in parallel.

When using a volatile FIFO, it is important to note that written data disappears after a certain period of time. There is no problem if the period of the signal 5ENB. is short, but since there is no guarantee, a non-volatile function (hereinafter referred to as "fresh") is provided to prevent data from disappearing.

Refresh is performed when signal 5BNB is @1'm.
, this is performed using a section in which the output image signal sequence is considered invalid. When the signal 5END becomes @1”, the current line FIF
O30 inputs the current line No. 1 column which is its output, and the previous line FIFO 40 inputs the previous line signal column which is its output. By doing this, the internal data of each FIFO is refreshed. The internal address of the FIFO immediately after layer number 5ENB becomes ``1'' points to a location that does not contain data.

When it reaches the maximum value, it returns to 10", and after that the written data is refreshed. Signal 8 ENB is 1"
Depending on the length of a certain section, not all data may be refreshed, but this is not a problem because such data has been written for a short time and does not require refreshing.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by using a line memory FIFO in a parallel image signal output circuit and providing a refresh function using a selector, data can be easily parallelized using a clock having the same frequency as the data. The effect is that the image signal can be controlled.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing one practical example of the present invention, and FIG.
The figure is a block diagram of a circuit according to the prior art.

Claims (1)

[Claims] An arbitrary multilevel image signal string inputted from the image signal reading section is output as the next line image signal string, and at the same time, the current line F
It connects to the data input of the IFO and outputs the data output of the current line FIFO as the current line image signal sequence, and at the same time connects to the data input of the previous line FIFO to output the data output of the current line FIFO as the current line image signal string.
means for outputting the data output as a previous line image signal sequence, a first control signal indicating a valid section of the multi-level image signal sequence, and a second control signal indicating an invalid section of the multi-level image signal sequence. means for inputting a reset pulse to a write address reset terminal and a read address reset terminal of the FIFO at the beginning of the first control signal;
a first selector for connecting the valid period of the first control signal to the next line image signal string and the valid period of the second control signal to the data input of the IFO; A second selector is provided for connecting the valid section of the first control signal to the current line signal string and the valid section of the second control signal to the data input of the previous line FIFO. A parallel image signal output circuit characterized by: