JPH05225319A - Signal delay circuit - Google Patents

Abstract

PURPOSE:To obtain a signal delay circuit where circuit scale is small and power consumption is small by providing plural shift registers and feeding time series signals circularly. CONSTITUTION:The signal delay circuit is provided with plural shift registers 31, a first switch 37 between a signal input line and the input terminal of the shift registers 31, a second switch 38 between the signal output line and the output terminal of the shift register 31, a clock generation circuit 35 feeding clock pulses circularly to the shift registers 31, an input switch circuit switching the first switch 37 so that the signals on the signal input line may be circularly inputted in the shift registers 31 and an output switch circuit switching the second switch 38 so that the output signal of the shift register 31 may be circularly outputted to the output line. By circularly inputting time series signals in plural shift, registers 31, the circuit scale is reduced and the circuit becomes a signal delay circuit 30 small in a chip area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal delay circuit most suitable for a line buffer used for image processing or the like.

[0002]

2. Description of the Related Art An image is raster-scanned and converted into a time-series digital signal such that one numerical value corresponds to each pixel forming the image, and this time-series digital signal is input. For example, various circuits for performing various image processing such as edge extraction processing and averaging processing are configured.

Here, in the case of performing various kinds of image processing as described above, for example, 3 × 3 with an arbitrary pixel on the image as a center.
Image processing is performed on the arbitrary pixels using digital signals corresponding to the pixels. In this case, it is necessary to collect nine digital signals corresponding to the 3 × 3 pixels from the digital signals input in time series at the same time. As a signal delay circuit for this purpose, a so-called dual port RAM or the like has been conventionally used.

FIG. 4 is a diagram schematically showing an example of the dual port RAM. For simplicity, each memory cell is 1
Of the two ports A and B, the A port is shown as a write-only port and the B port is shown as a read-only port. The dual port RAM 1 has n × m memory cells 10 arranged in the horizontal direction n and the vertical direction m.
Is provided. Here, an address indicating one of the memory cells 10 to which data is to be written is input from the A port address input terminal 11, and at the same time,
Write data (here, 1-bit data) to be written to the memory cell indicated by the address is input from the A port data input terminal 12. The write data input from the A port data input terminal 12 is input to the A port column selector 14 via the A port write amplifier 15. It is assumed here that the address data of the memory cell at the upper left corner of FIG. 4 is input from the A port address input terminal 11. This A port address input terminal 11
The address data input from is input to the A port row decoder 13 and the A port column selector 14.
The A-port row decoder 13 recognizes the address in the vertical direction in the drawing in which the selected memory cell is arranged from the input address data, and the corresponding word line W ₀ A, ..., W
_{One of m-1} A (here, word line W ₀ A) has'H
Output the'level 'signal. In addition, the A port column selector 14 selects A based on the input address data.
A bit line pair bitoA, bi from which the write data input from the port data input terminal 12 and input to the A port column selector 14 via the A port write amplifier 15 should be output.
toA ';...; Select bit _n-1 A, bit _n-1 A'. Here, the bit line pair bitoA and bitoA 'are selected, and the bit line bi
The write data is output to toA, and the data of the logic level opposite to the write data is output to bitoA '. In this way, the A-port row decoder 13 outputs an “H level” signal to the word line W ₀ A, whereby the gate transistor 1
0a is turned on, and the data is output to the bit line pair bitoA and bitoA '.
The data of A and bito A'is taken into the memory cell 10,
After that, when the word line W ₀ A changes to the “L level”, the input data is stored in the inverter 10b.

On the other hand, at the time of reading, address data of the memory cell 10 (here, the upper leftmost memory cell in FIG. 1) whose contents are to be read is input from the B port address input terminal 16. This address data is input to the B port row decoder 17 and the B port column selector 18, and the B port row decoder 17 outputs an “H level” signal to the word line W ₀ B. The bit line pair bitoB and bitoB ′ are connected to the B port sense amplifier 19. In this way, the B-port row decoder 17 outputs the signal at the “H level” to the word line W ₀ B, whereby the gate transistor 10c is turned on and the data stored in the memory cell 10 becomes bit line pair bitoB. , BitoB ′, and is output to the outside from the B port data output terminal 20 via the B port sense amplifier 19.

FIG. 5 shows the dual port RAM shown in FIG.
FIG. 3 is a circuit block diagram when is used as a signal delay circuit. The clock signal CLK is input to the address generation circuit 2, and the clock pulse 1 of the clock signal CLK is input to the dual port RAM 1 from the A port address input terminal 11.
An address that is incremented one by one is input, and the same address that is input to the A port address input terminal 11 is input to the B port address input terminal 16 at a timing delayed by a predetermined delay amount. ..
When the addresses of the A port address input terminal 11 and the B port address input terminal 16 reach the address m × n, the address 1 is returned to next.

When the time series data DATA-IN is input from the A port data input terminal 12 in synchronization with the address input to the A port address input terminal 11,
This data DATA-IN is time-delayed by a predetermined number of clock pulses, and time-series data DATA-OUT is output from the B port data output terminal 20, whereby the time-series signal is delayed.

[0008]

As described above, the time-series signal can be delayed by using the dual port RAM, but when this dual port RAM is used for the signal delay, it is compared with its function. There are problems that the chip area is large and the power consumption is large. In view of this problem, it is an object of the present invention to provide a signal delay circuit having a smaller chip area and lower power consumption than the above dual port RAM.

[0009]

A first signal delay circuit of the present invention for achieving the above object comprises a plurality of shift registers, a signal input line shared by the plurality of shift registers, and the signal input. A plurality of first switches arranged between the lines and the input terminals of the plurality of shift registers, a signal output line shared by the plurality of shift registers, and a signal output line of the plurality of shift registers. A plurality of second switches arranged between the output terminals, a clock generation circuit that cyclically sends a clock pulse to all or some of the plurality of shift registers, and a signal on the signal input line has a plurality of signals. An input switching circuit that cyclically switches the plurality of first switches to a conductive state so as to be cyclically input to all or part of the shift register; and all or part of the plurality of shift registers. Force signal is characterized in that an output switching circuit for switching the cyclically conducting state the plurality of second switches so as to be cyclically output to the signal output line.

It is preferable that the input switching circuit and the output switching circuit are included in the clock generation circuit. That is, the second signal delay circuit of the present invention configured as described above includes a plurality of shift registers, a signal input line shared by the plurality of shift registers, the signal input line and the plurality of shift registers. A plurality of first switches arranged between the input terminals and having control terminals connected to the clock lines of the corresponding shift register, a signal output line shared by the plurality of shift registers, and the signal output line And a plurality of second switches, the control terminals of which are arranged between the output terminals of the plurality of shift registers and whose control terminals are connected to the clock lines of the corresponding shift registers,
A clock generation circuit for cyclically sending clock pulses to all or part of the plurality of shift registers is provided.

[0011]

When the above-mentioned dual port RAM is used, it is possible to delay by an arbitrary number of clock pulses within the number of memory cells. However, the signal delay circuit as a line buffer used for image processing etc. Various changes are extremely rare, and it is often sufficient to be able to delay by a predetermined clock pulse.

In consideration of this point, the present invention is provided with a plurality of shift registers, and is configured to cyclically input time-series data to the plurality of shift registers, whereby the above dual port RAM is provided. Compared with the above, the number of bit lines is significantly reduced, whereby the column selector can be simplified or omitted, and the number of word lines is also reduced and the row decoder is also simplified. As described above, the signal delay circuit of the present invention has a reduced circuit scale and a small chip area. In addition, the power consumption of the entire circuit is reduced due to the reduction of the power consumption due to the reduction of the circuit scale and the reduction of the power consumption for the precharge due to the significant reduction of the number of bit lines. ..

[0013]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic diagram of a signal delay circuit according to an embodiment of the present invention. Here, as in the case of the conventional example (see FIG. 4), for the sake of simplicity, it is assumed that each memory cell (each flip-flop) holds 1-bit data.

The signal delay circuit 30 includes n dynamic flip-flops 32, ... 32 arranged side by side in FIG.
An n-bit shift register 31 is configured by, and m shift registers 31 having the same configuration are arranged in the vertical direction of FIG. Address data for selecting one of the m shift registers 31 (here, the shift register arranged at the top of FIG. 1) from the address input terminal 33 provided commonly to both the A port and the B port. Is input, and write data to be written to the shift register 31 indicated by the address from the A port data input terminal 34 (here, 1-bit data).
Is entered.

In the A and B port row decoder 35, based on the address data input from the address input terminal 33, here, an "H level" signal is output to the word line W ₀ . The write data input from the A port data input terminal 34 is output to the bit line bit A via the A port write amplifier 36. In this way, the signal of'H level 'is output from the A, B port row decoder 35 to the word line W ₀ , whereby the gate transistor 37 which is an example of the first switch according to the present invention is turned on, and the bit transistor 37 is turned on. The signal on line bit A is taken into the top shift register shown in FIG. 1 from its left end. Each word line W ₀ in the above manner, ..., W _m-1 are sequentially selected, the word line W _m-1 of the next return to the word lines W _0, thus the word lines W _0, ..., W _{When m-1} is cyclically selected and time-series data is input in synchronization with this, shift registers 31, ..., 31 provided with m pieces of this time-series data.
Then, each pixel is sequentially and cyclically input.

As described above, the time-series data of m × n pixels are sequentially input to and stored in the signal delay circuit 30, the m × n + 1th data is input next, and the word line W ₀ is'H '. When the level 'signal is output, the gate transistor 37 is turned on, the m × n + 1th data is input to the shift register 31, and the gate transistor 38 at the right end (second in the present invention).
Data input terminal 3
The write data input first from 4 is output to the bit line bit B via the gate transistor 38,
Data output terminal 4 via B port sense amplifier 39
It is output from 0 to the outside, and thereafter, the second, third, ...
The write data input to is output in time series.

FIG. 2 is a schematic diagram of a signal delay circuit according to another embodiment of the present invention. Here, as in the case of the conventional example (see FIG. 4) and the above-described embodiment (see FIG. 1),
Description will be made assuming that each memory cell (each flip-flop) holds 1-bit data. Moreover, this FIG.
In FIG. 1, the components corresponding to the components of the above-described embodiment (see FIG. 1) are denoted by the same numbers as those given in FIG. 1 for simplicity, regardless of the difference in the detailed circuit configuration. , And detailed description is omitted.

Although each flip-flop 32 shown in FIG. 1 is a dynamic circuit, the flip-flop 32 as a static circuit is provided in this FIG. As described above, the present invention can be applied to both dynamic and static circuit systems. FIG. 3 is a circuit block diagram configured to delay a signal using the signal delay circuit shown in FIG. 1 or 2.

The clock signal CL is sent to the address generation circuit 50.
K is input, the clock signal CLK is counted by a modulo m counter (a counter configured to return to 1 and continue counting again at the next clock pulse after counting up to m), and the output of this counter is a signal delay circuit. Input from the address input terminal 33 of 30. As a result, an "H level" signal is cyclically output from the A and B port row decoder 35 shown in FIGS. 1 and 2 to each of the word lines W _{0 to} W _{m- 1.} To be done. When the time series data DATA-IN is input from the data input terminal 34 in synchronization with the counter output input from the address input terminal 33, the time series data DATA-IN is input from the data output terminal 40 to the clock pulse m ×. Time-series data D delayed by n
ATA-OUT is output, which delays the time series signal.

Thus, in the embodiment shown in FIGS. 1 and 2, n
By adopting a configuration in which m stages of shift registers 31 are provided, column selectors are omitted, the row decoder is simplified, and the number of word lines and bit lines is reduced as compared with the conventional example (see FIG. 4). Thus, a signal delay circuit having a small circuit scale and low power consumption is configured. Here, it is possible to provide one shift register of m × n stages, but in this case, data of a very large number of stages of m × n stages are simultaneously shifted for each clock pulse, and the power consumption is rather increased. Will increase.

In each of the above embodiments, the data input terminal 34
The data input from is the number of clock pulses and is m × n
Output from the data output terminal 40 after being delayed by
Instead of sequentially and cyclically setting the word lines W _{0 to} W _m-1 to'H level ', for example, by sequentially and cyclically setting the word lines W _{0 to} W _m-2 to'H level' (m-1 ) × n delayed data can be obtained, for example word line W ₀
It is possible to obtain data delayed by (m−2) × n by sequentially setting ~ W _m−3 to'H level 'cyclically.

In each of the above embodiments, only the output of the final stage of the shift register is taken out, but the present invention is not limited to this. For example, the number of bit lines on the B port side is increased and the shift register 31 is provided. The output may be obtained from the middle stage. Further, in each of the above-described embodiments, the gate transistors 37 and 38 are connected to the clock line of the shift register 31 and turned on / off by a clock pulse.
Although it is turned off, it is not necessarily connected to the clock line and may be controlled separately from the clock pulse.

[0023]

As described in detail above, the signal delay circuit of the present invention is provided with a plurality of shift registers, and the time series signals are cyclically sent to these plurality of shift registers. Therefore, the circuit scale is small. Moreover, a signal delay circuit with low power consumption is realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a signal delay circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a signal delay circuit according to another embodiment of the present invention.

FIG. 3 is a circuit block diagram configured to delay a signal using the signal delay circuit shown in FIGS. 1 and 2.

FIG. 4 is a diagram schematically showing an example of a dual port RAM.

5 is a circuit block diagram when the dual port RAM shown in FIG. 4 is used as a signal delay circuit.

[Explanation of symbols]

 30 signal delay circuit 31 shift register 37, 38 gate transistor 33 address input terminal 34 data input terminal 40 data output terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 11/401

Claims (2)

[Claims] 1. A plurality of shift registers, a signal input line shared by the plurality of shift registers, and a plurality of first input terminals arranged between the signal input line and each input terminal of the plurality of shift registers. A switch, a signal output line shared by the plurality of shift registers, a plurality of second switches arranged between the signal output line and each output terminal of the plurality of shift registers, and the plurality of shift registers A clock generation circuit that cyclically sends a clock pulse to all or part of the plurality of shift registers, and the plurality of first switches so that the signal on the signal input line is cyclically input to all or part of the plurality of shift registers An input switching circuit that cyclically switches the plurality of shift registers to a conductive state, and a plurality of the second shift circuits so that all or some of the output signals of the shift registers are cyclically output to the signal output line. Signal delay circuit, characterized in that an output switching circuit for switching the cyclically conducting state switch. 2. A plurality of shift registers, a signal input line shared by the plurality of shift registers, and a control terminal arranged between the signal input line and each input terminal of the plurality of shift registers. A plurality of first switches connected to corresponding clock lines of the shift register, a signal output line shared by the plurality of shift registers, and between the signal output line and each output terminal of the plurality of shift registers A plurality of second switches, which control terminals are connected to corresponding clock lines of the shift register, and a clock generation circuit which cyclically sends clock pulses to all or part of the plurality of shift registers. A signal delay circuit characterized by being provided.