CN115269491B - Single-wire communication device and single-wire communication method - Google Patents
Single-wire communication device and single-wire communication method Download PDFInfo
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- CN115269491B CN115269491B CN202210843767.5A CN202210843767A CN115269491B CN 115269491 B CN115269491 B CN 115269491B CN 202210843767 A CN202210843767 A CN 202210843767A CN 115269491 B CN115269491 B CN 115269491B
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- 238000004891 communication Methods 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000012545 processing Methods 0.000 claims abstract description 41
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 9
- 230000004044 response Effects 0.000 claims description 2
- 238000005070 sampling Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000009966 trimming Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
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- 230000005540 biological transmission Effects 0.000 description 2
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30141—Implementation provisions of register files, e.g. ports
Abstract
The invention discloses a single-wire communication device and a single-wire communication method, relates to the technical field of communication, and aims to solve the problem that an existing chip can communicate only by a clock. The single-wire communication device includes: the system comprises an upper computer, a signal generating module, a data processing circuit and a drain pipe; the upper computer is used for controlling the signal generating module to generate a data pulse signal, the data processing circuit comprises a decoding circuit and a clock generating circuit, the decoding circuit is used for decoding the data pulse signal into a high level or a low level, the clock generating circuit is used for converting the data pulse signal into a clock signal and sending the clock signal to the shift register module, and the shift register module is used for sampling or holding the high level or the low level based on the clock signal to finish data writing; the open drain pipe is used for returning the chip data. The single-wire communication device and the single-wire communication method can be realized without an internal clock.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a single-wire communication device and a single-wire communication method.
Background
The most commonly used single-Wire communication method is a 1-Wire protocol defined by Dallas corporation in a DS18B20 temperature sensor, and compared with the traditional two-Wire system (I2C), three-Wire System (SPI) and other communication methods, the method has the greatest advantage of saving pins and wiring resources.
The general analog chip needs to be calibrated, and the final trimming control word is confirmed and written into the chip. Since the influence of the package on the chip is great, the chip is generally calibrated after the package. Additional pins are required for communication when calibrating the analog chip, and single-wire communication is the best choice for reducing pin resource occupation.
In the existing single-wire communication method, a chip needs to have a clock to communicate, and an extra pin is needed for single-wire communication. However, the clock introduces additional power consumption and produces interference with other analog circuits; in addition, for the analog chip, the size is generally smaller, and the pin resources are relatively tense, so that the existing single-wire communication method is difficult to apply to the analog chip.
Disclosure of Invention
The invention aims to provide a single-wire communication device and a single-wire communication method, which are used for solving the problems that an existing chip can communicate only by a clock and the single-wire communication needs to occupy extra pins.
In order to achieve the above object, the present invention provides the following technical solutions:
in one aspect, the present invention provides a single-wire communication device, at least comprising: the system comprises an upper computer, a signal generating module, a data processing circuit and a drain pipe;
the upper computer is in communication connection with the signal generation module, the signal generation module is in communication connection with the data processing circuit through a port of the chip, and the data processing circuit is in communication connection with the open drain pipe;
the upper computer is used for controlling the signal generation module to generate a data pulse signal, the data processing circuit comprises a decoding circuit and a clock generation circuit, the decoding circuit is used for decoding the data pulse signal into a high level or a low level, the clock generation circuit is used for converting the data pulse signal into a clock signal and sending the clock signal to the shift register module, and the shift register module is used for sampling or holding the high level or the low level based on the clock signal to finish data writing;
the drain electrode of the open drain pipe is connected with the port of the chip, and the open drain pipe is used for returning the chip data through the port of the chip.
In another aspect, the present invention provides a single-wire communication method, which is applied to the single-wire communication device, and includes:
acquiring an operation instruction, wherein the operation instruction is a write-in data instruction or a read-out data instruction;
when the operation instruction is a data writing instruction, controlling the signal generating module to generate a data pulse signal of data to be written, wherein the first bit and the last bit of the data to be written are both 1;
a decoding circuit in the data processing circuit decodes the data pulse signal of the data to be written into a high level or a low level;
a clock generating circuit in the data processing circuit generates a clock signal based on the data pulse signal and sends the clock signal to a shift register module in the data processing circuit;
the shift register module samples or holds the high level or the low level based on the clock signal to complete data writing;
and when the operation instruction is a data reading instruction, controlling the open drain pipe to return the chip data.
Compared with the prior art, the single-wire communication device provided by the invention comprises the following components: the system comprises an upper computer, a signal generating module, a data processing circuit and a drain pipe; the upper computer is in communication connection with the signal generation module, the signal generation module is in communication connection with the data processing circuit through a port of the chip, and the data processing circuit is in communication connection with the open drain pipe; the upper computer is used for controlling the signal generation module to generate a data pulse signal, the data processing circuit comprises a decoding circuit and a clock generation circuit, the decoding circuit is used for decoding the data pulse signal into a high level or a low level, the clock generation circuit is used for converting the data pulse signal into a clock signal and sending the clock signal to the shift register module, and the shift register module is used for sampling or holding the high level or the low level based on the clock signal to finish data writing; the drain electrode of the open drain pipe is connected with the port of the chip, and the open drain pipe is used for returning the chip data through the port of the chip. The clock generating circuit generates clock signals based on the data pulse signals to replace the devices of the existing chip for generating clocks, so that extra power consumption caused by the clocks and interference of an analog circuit are reduced, a decoding circuit decodes the data pulse signals into high level or low level, the clock generating circuit generates clock signals, a shift register realizes sampling and holding of the data pulse signals based on the clock signals, data writing is realized, whether transmission of the data pulse signals or return data of an open drain pipe are communicated through ports of the chip, communication is completed by using a single wire, writing and reading of data of the chip are realized, and when the clock generating circuit is applied to the analog chip, pins of the ports can be shared with other analog pins without extra pins for communication.
According to the single-wire communication method provided by the invention, the decoding circuit in the data processing circuit is controlled to decode the data pulse signal of the data to be written into the high level or the low level according to the data writing instruction, the clock generating circuit generates the clock signal and sends the clock signal to the shift register module, the shift register module samples and holds the high level or the low level based on the clock signal, the writing of the data to be written is completed, the open drain pipe is controlled to complete the chip data return according to the data reading instruction, and therefore the writing and the reading of the data of the chip are realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a block diagram of a single-wire communication device according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a data processing circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an embodiment of a clock generation circuit according to the present invention;
FIG. 4 is a schematic diagram of waveforms of data pulse signals of data 0 and data 1 according to an embodiment of the present invention;
FIG. 5 is a diagram of an example 10bit data input provided by an embodiment of the present invention;
FIG. 6 is a diagram illustrating an example of data reading according to an embodiment of the present invention;
fig. 7 is a flowchart of a single-wire communication method according to an embodiment of the present invention.
Reference numerals:
the device comprises a 1-upper computer, a 2-signal generating module, a 3-first switch, a 4-second switch, a 5-pull-up resistor, a 6-data processing circuit, a 7-open drain pipe, an 8-decoding circuit, a 9-clock generating circuit, a 10-shift register module, an 11-first resistor, a 12-second resistor, a 13-third switch, a 14-fourth switch and a 15-first comparator.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
In the manufacturing of analog chip, need mark before dispatching from the factory, change the inside trimming control word of chip, current single line communication device needs extra pin to communicate, and needs the chip to contain the internal clock and just can communicate, however analog chip is because the size is little, and pin resource is tension, and the clock can bring extra consumption and exert an influence to analog circuit, therefore current single line communication device is unsuitable for analog chip.
In view of the above, the present invention proposes a single-wire communication device and a single-wire communication method. The following description is made with reference to the accompanying drawings.
Fig. 1 is a block diagram of a single-wire communication device according to an embodiment of the present invention, where the device shown in fig. 1 includes: the device comprises an upper computer 1, a signal generating module 2, a first switch 3, a second switch 4, a pull-up resistor 5, a data processing circuit 6 and an open drain pipe 7;
the upper computer 1 is in communication connection with the signal generating module 2, the signal generating module 2 is in communication connection with the data processing circuit 6 through a port of the chip, and the data processing circuit 6 is in communication connection with the open drain pipe 7; the pull-up resistor 5 is connected with the first switch 3 in series, the pull-up resistor 5 is connected with the power VCC, the first switch 3 is connected with the port of the chip, the second switch 4 is connected with the output end of the signal generating module 2, the second switch 4 is connected with the port of the chip, and the second switch 4 is connected with the first switch 3 in parallel;
the upper computer 1 is used for controlling the signal generating module 2 to generate a data pulse signal, the data processing circuit 6 comprises a decoding circuit 8 and a clock generating circuit 9, the decoding circuit 8 is used for decoding the data pulse signal into a high level or a low level, the clock generating circuit 9 is used for converting the data pulse signal into a clock signal and sending the clock signal to the shift register module 10, the shift register module 10 samples or holds the high level or the low level based on the clock signal to finish data writing, at the moment, the first switch 3 is opened, the second switch 4 is closed, and the signal generating module 2 is communicated with the data processing circuit 6;
the drain electrode of the open drain pipe 7 is connected with the port of the chip, the open drain pipe 7 is used for returning chip data through the port of the chip, at the moment, the first switch 3 is closed, the second switch 4 is opened, and the pull-up resistor 5 is matched with the open drain pipe 7 to realize data return.
The data processing circuit 6 and the open drain pipe 7 are both chip internal structures.
The upper computer 1 can be a computer, a CPU or a controller, etc.
The signal generating module 2 may be a signal generator or a waveform generating circuit, fig. 1 shows a structure of the waveform generating circuit, and as shown in fig. 1, the waveform generating circuit may include a first resistor 11, a second resistor 12, a third switch 13 and a fourth switch 14, where the first resistor 11 is connected in series with the second resistor 12, the first resistor 11 is connected in series with the third switch 13, the third switch 13 is connected to a power VCC, the second resistor 12 is connected in series with the fourth switch 14, the fourth switch 14 is grounded, and an output terminal of the signal generating module 2 is intermediate between the first resistor 11 and the second resistor 12.
The first switch 3, the second switch 4, the third switch 13 and the fourth switch 14 can be common single pole single throw switches or electronic switches.
The resistance of the pull-up resistor 5 may be selected between 1k ohms and 10k ohms, and the resistance values of the first resistor 11 and the second resistor 12 are the same.
The configuration data processing circuit 6 in fig. 1 can be described with reference to fig. 2, as shown in fig. 2, the clock generating circuit provides clock signals for the shift register module 10, the decoding circuit 8 is connected to the input end of the shift register module 10, the shift register module 10 includes N shift registers, N is the same as the bit number of the data to be written, when Nbit is transmitted, at least N D flip-flops are required to be connected in series, each flip-flop is 1 shift register, and receives a common clock signal, and the clock signal is generated by the clock generating circuit 9. Specifically, the data 0 or the data 1 is required to be obtained by a decoding circuit 8 to be low level or high level, and the data is sequentially transferred to the next shift register based on a clock signal, and Q [ N:0 is the parallel output of the data. The data writing can be accomplished by the data processing circuit.
The clock generation circuit 9 may be implemented by a circuit that can decode a data pulse signal into a clock signal that varies from a low level to a high level, or may be implemented by a comparator, as illustrated in fig. 3, and includes a first comparator 15, for example, when the data to be written is "100", the data pulse signal is input to the first comparator 15, and compared with vcc×3/4 to generate a Z1 signal as illustrated in fig. 3, and the Z1 signal is selected as the clock signal, where vcc×3/4 is a threshold voltage of the first comparator, and the threshold voltage of the first comparator 15 is higher than the voltage value of the first potential; the first potential defines the potential of data 1 in the data pulse signal. The threshold voltages of the two comparators may be changed as desired. In the prior art, a clock circuit which specially generates a clock signal inside a chip is generally an oscillator formed by ring oscillators to generate the clock signal, and the clock circuit not only can bring additional power consumption, but also can influence an analog circuit.
The decoding circuit 8 is a circuit for decoding the data pulse signal into a high level or a low level, and may be implemented by using one comparator, or may be implemented by using another decoding circuit, where the threshold voltage of the comparator is lower than the voltage value of the first potential, and VCC 1/4, VCC 1/5, or the like may be selected.
The open drain tube 7 can be an NPN transistor or an NMOS transistor, and the open drain circuit is used for connecting devices with different levels and is used for matching the levels, because the open drain pin can only output a low level when not connected with an external pull-up resistor, if the open drain pin needs to have a function of outputting a high level at the same time, the pull-up resistor needs to be connected, as shown in fig. 1, when the first switch 3 is closed, the pull-up resistor 5 is connected with the open drain tube 7, and the transmission level can be changed by changing the voltage of the pull-up power supply, and further, the data return of the chip is realized by the cooperation of the open drain tube 7 and the pull-up resistor 5.
The data processing circuit 6 or the open drain pipe 7 is subjected to logic control and/or output control in the chip to realize data writing or data returning.
The port of the chip is a communication pin of the chip, the communication pin can be shared with other analog pins, the pin can be a digital IO pin during calibration, and after the test is finished, a specific instruction is written or a value stored in a specific position is changed to enable the digital IO function to be closed. This allows digital communication to be accomplished in certain situations without taking up additional pins.
In the structure shown in fig. 1, clock signals are generated by the clock generating circuit 9 based on data pulse signals to replace clocks in chips in the prior art, so that extra power consumption caused by the clocks and interference of an analog circuit are avoided, the data pulse signals are decoded into high level or low level by the decoding circuit 8, the clock signals are generated by the clock generating circuit 9, the data pulse signals are sampled and held by the shift register module 10 based on the clock signals, data writing is realized, data is returned through the open drain pipe 7, and whether the data pulse signals are transmitted or the data returned by the open drain pipe 7 are communicated through ports of the chips, communication can be completed by using a single wire, writing or reading of the data of the chips is realized, and pins of the ports can be shared with other analog pins without extra pins for communication when the clock generating circuit is applied to the analog chip.
Based on the scheme of fig. 1, embodiments of the present invention also provide some specific implementations of the scheme, and are described below.
The single-wire communication device has two working states of writing data and reading data, wherein the writing data state is described first, at the moment, the second switch 4 is in a closed state, the first switch 3 is in an open state, and the opening or closing of the first switch 3 and the second switch 4 can be controlled by the upper computer 1 or by a program.
After the VCC/2 potential t is kept for a time when the data pulse signal is kept, the VCC potential t is kept continuously for a time, and writing 1 is completed; after the data pulse signal keeps the GND potential t for a while, the VCC potential t is kept for a while, and the writing of 0 is completed. The data pulse signals corresponding to data 1 and data 0 are shown in fig. 4. The data pulse signal of the data 1 changes from VCC/2 potential to VCC potential, and the data pulse signal of the data 0 changes from GND potential to VCC potential; the time parameter t depends on the port data response time of the chip, and the smaller the chip process size is, the smaller the value of t can be.
The VCC/2 potential is used to define the data 1, and the data 1 may be defined by other potentials, and it should be noted that the potential defining the data 1 needs to be selected in the middle area of two threshold voltages of two comparators in the clock generating circuit 9, so that a clock signal may be generated, for example: when the two threshold voltages are vcc×3/4 and vcc×1/4, vcc×2/3 or vcc×3/5 may be selected to define data 1. The GND potential is used to define data 0.
The generation of the above-described data pulse signal may be described with reference to fig. 1, referring to fig. 1, when the third switch 13 and the fourth switch 14 are closed, the VCC/2 voltage is outputted; when the third switch 13 is closed and the fourth switch 14 is opened, the VCC/2 voltage is outputted; when the third switch 13 is opened and the fourth switch 14 is closed, the GND voltage is output.
Specifically, since there is no internal clock, data 0 and data 1 are sampled and held by the chip in 2 t. The first t time is the data sampling stage, the decoding circuit 8 decodes the VCC/2 potential into data 1, and the GND potential into data 0; the second time t is a data holding stage, and since the voltage is changed from VCC/2 or GND to VCC, the clock generating circuit 9 can decode the standard clock signal changed from low level to high level and send the signal to the shift register module 10, thereby completing the data sampling holding process, i.e. low level sampling, high level holding, and completing the data writing.
Next, a data reading process of reading chip data will be described, and the present single-wire communication device returns data through the open drain pipe 7.
Specifically, the single-wire communication device provides a 1bit reading mechanism, referring to fig. 1, after the upper computer 1 sends data to the chip through the signal generating module 2, the second switch 4 is opened, so that the signal generating module 2 is disconnected from the port of the chip, and meanwhile, the first switch 3 is closed, so that the pull-up resistor 5 is connected to the port of the chip. The chip returns data outwards through the open drain pipe 7, if the chip returns data 1, the grid of the open drain pipe in the chip is at a low level, the open drain pipe 7 is cut off, and the port of the chip is pulled to a high level by the pull-up resistor 5; if the chip returns data 0, the gate of the open drain pipe 7 in the chip is at high level, the open drain pipe 7 is conducted, and the port of the chip is pulled to low level by the pull-up resistor 5. Since there is no internal clock, only 1bit of data can be returned at a time. The data will remain output until no new data is written to the chip. When new data is written, in the first t time, the last written data is still stored in the shift register module in the first t time, that is, the state that the chip outputs is kept, so that when the chip outputs, new data pulse signals are simultaneously input, if the open drain tube 7 of the chip is pulled down, if the on resistance of the pull-down drain tube 7 is small, when the data 1 is written in next, VCC/2 potential is normally generated in the first t time, but when the open drain tube 7 is still pulled down, the level which is supposed to be VCC/2 potential is pulled to be very low, so that the chip is misidentified, that is, the data 1 is misidentified as the data 0, and communication is affected, so that the on resistance of the open drain tube 7 in the chip must be very large.
Based on the single-wire communication device, the invention also provides a single-wire communication method, which is applied to the single-wire communication device, wherein the device at least comprises an upper computer, a signal generating module, a data processing module and an open drain pipe, and is described with reference to fig. 7, and the method comprises the following steps:
step 701: and acquiring an operation instruction.
The operation instruction is a write-in data instruction or a read-out data instruction, and the operation instruction can be acquired by the upper computer.
Step 702: when the operation instruction is a data writing instruction, the signal generating module is controlled to generate a data pulse signal of data to be written.
When writing data, the data is stored in the chip through the shift register module, before the data is written into the chip each time, the data 0 with the same number as the number of the data bits to be written is transmitted to the chip, and the data is cleared, so that the internal shift register module can be cleared. Since the chip reads the value of the shift register in the chip in real time, other specific instructions cannot be prevented from being triggered by mistake, specific processing is required, the first bit and the last bit of data to be written are required to be 1, 10bit data are shown in fig. 5, and D [0] and D [9] are both 1, so that the situation of data erroneous writing can be avoided.
Step 703: a decoding circuit in the data processing circuit decodes the data pulse signal of the data to be written into a high level or a low level.
Data 1 is decoded high and data 0 is decoded low. The data processing circuit can be controlled by a logic control unit in the chip or by an upper computer.
Step 704: a clock generation circuit in the data processing circuit generates a clock signal based on the data pulse signal and transmits the clock signal to a shift register module in the data processing circuit.
Step 705: and the shift register module samples or holds the high level or the low level based on the clock signal to complete data writing.
High level sampling, low level holding.
Step 706: and when the operation instruction is a data reading instruction, controlling the open drain pipe to return the chip data.
The open drain pipe can only return 1bit data each time, the data reading can be described with reference to FIG. 6, as shown in FIG. 6, the upper computer sends a data pulse signal of 10bit data to the chip, the chip samples and holds the data pulse signal to obtain parallel data from D0 to D9, the data is stored in the shift register module, and the data writing is completed, wherein, both D0 and D9 are 1; when the data needs to be read, the address of the data to be read in the chip is positioned according to the data reading instruction, the chip returns the data of the address, and 1bit of data is returned each time.
In the method shown in fig. 7, a decoding circuit in a data processing circuit is controlled to decode a data pulse signal of data to be written into a high level or a low level according to a data writing instruction, a clock generating circuit generates a clock signal and sends the clock signal to a shift register module, the shift register module samples and holds the high level or the low level based on the clock signal to complete writing of the data to be written, and a drain pipe is controlled to complete data return according to a data reading instruction, so that writing and reading of the data of a chip are realized.
The single-wire communication device and the single-wire communication method can be applied to an analog chip and used for changing the trimming control word in the chip, the trimming control word is generally only used when the chip is calibrated in a factory, and the chip cannot be communicated after the trimming control word is manufactured.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A single wire communication device comprising at least: the system comprises an upper computer, a signal generating module, a data processing circuit and a drain pipe;
the upper computer is in communication connection with the signal generation module, the signal generation module is in communication connection with the data processing circuit through a port of the chip, and the data processing circuit is in communication connection with the open drain pipe;
the upper computer is used for controlling the signal generation module to generate a data pulse signal, the data processing circuit comprises a decoding circuit and a clock generation circuit, the clock generation circuit comprises a first comparator, the threshold voltage of the first comparator is higher than the voltage value of a first potential, and the first potential is the initial potential of definition data 1 in the data pulse signal; the decoding circuit comprises a second comparator, wherein the threshold voltage of the second comparator is lower than the voltage value of the first potential; the decoding circuit is used for decoding a first potential in the data pulse signal into a high level, decoding a GND potential into a low level, the clock generating circuit is used for converting the data pulse signal into a clock signal and sending the clock signal to the shift register module, and the shift register module samples or holds the high level or the low level based on the clock signal to finish data writing;
the drain electrode of the open drain pipe is connected with the port of the chip, and the open drain pipe is used for returning the chip data through the port of the chip.
2. The single wire communication device of claim 1, further comprising a pull-up resistor and a first switch, the pull-up resistor being in series with the first switch, the pull-up resistor being connected to a power source, the first switch being connected to a port of the chip; when the open drain pipe returns data, the first switch is closed, and the pull-up resistor is matched with the open drain pipe to realize data return.
3. The single wire communication device of claim 2, wherein when the open drain return data is 1, the gate of the open drain is low, the open drain is off, and the port of the chip is pulled high; when the return data is 0, the grid electrode of the open drain pipe is high level, the open drain pipe is conducted, the port of the chip is pulled to low level, and the open drain pipe returns 1bit data each time.
4. The single wire communication device of claim 2, further comprising a second switch coupled to an output of the signal generating module, the second switch coupled to the port of the chip, the second switch coupled in parallel with the first switch, the signal generating module in communication with the data processing circuit when the second switch is closed.
5. The single wire communication device of claim 1, wherein the signal generating module is a waveform generating circuit comprising a first resistor, a second resistor, a third switch and a fourth switch, the first resistor being in series with the second resistor, the first resistor being in series with the third switch, the third switch being connected to a power supply, the second resistor being in series with the fourth switch, the fourth switch being grounded, the output of the signal generating module being intermediate the first resistor and the second resistor.
6. The single wire communication device according to claim 1, wherein writing 1 is completed after the data pulse signal is held at the first potential t for a first time and then held at the VCC potential t for a second time; after the data pulse signal keeps GND potential t for a period of time, keeping VCC potential t for a period of time, and finishing writing 0; the time parameter t depends on the port data response time of the chip.
7. The single wire communication device of claim 1, wherein the number of shift registers in the shift register module is the same as the number of bits of data to be written.
8. A single-wire communication method, characterized in that it is applied to the single-wire communication device of any one of claims 1 to 7, the single-wire communication device at least includes a host computer, a signal generating module, a data processing circuit, and an open drain pipe, the method includes:
acquiring an operation instruction, wherein the operation instruction is a write-in data instruction or a read-out data instruction;
when the operation instruction is a data writing instruction, controlling the signal generating module to generate a data pulse signal of data to be written, wherein the first bit and the last bit of the data to be written are both 1;
a decoding circuit in the data processing circuit decodes the data pulse signal of the data to be written into a high level or a low level;
a clock generating circuit in the data processing circuit generates a clock signal based on the data pulse signal and sends the clock signal to a shift register module in the data processing circuit;
the shift register module samples or holds the high level or the low level based on the clock signal to complete data writing;
and when the operation instruction is a data reading instruction, controlling the open drain pipe to return the chip data.
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