JPH11282650A - Hazard prevention circuit for fifo memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a full signal and an empty signal without generating hazard. SOLUTION: Flags are set up correspondingly to respective addresses in a first in first out(FIFO) memory 11. When data are written in a certain address, tire flag corresponding to the address is set up to '1', and at the time of reading out data from a certain address, the flag corresponding to the address is set up to '0'. All outputs from the FIFO memory 11 are inputted to an AND circuit 14 and a NAND circuit 15, and a full signal and an empty signal are respectively outputted from the outputs of these, circuits 14, 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a hazard prevention circuit for a FIFO memory.

[0002]

2. Description of the Related Art A FIFO (First In First Out) memory is a first-in, first-out type memory in which data is read out in a written order. FIG. 3 shows a method of controlling reading and writing of data in such a memory.
In FIG. 3, a write counter 2 and a read counter 3 are connected to the FIFO memory 1 and controlled by a memory control unit (not shown). When writing data, the data is written to the address indicated by the write counter 2. Now, data 0 is address 0
When data 1 is written to address 1 and data 2 is written to address 2, the value of write counter 2 is incremented by one each time. When data N is written to last address N, the FIFO memory 1 is full. On the other hand, when reading data, the data is read from the address indicated by the read counter 3. When the value of the read counter 3 is 0, data 0 written at the address 0 is read, and when the value of the read counter 3 is 1, data 1 written at the address 1 is read. When the value of the read counter 3 is 2, the data 2 written at the address 2 is read,
Each time the value of the read counter 3 increases by one, and when the data N of the last address N is read, the FIFO memory 1 enters an empty state.

The determination of the full state and the empty state of the FIFO memory 1 is performed by comparing the respective outputs of the write counter 2 and the read counter 3 with the comparator 4. That is, the comparator 4 compares the value of the write counter 2 indicating the address at which the last write was performed with the value of the read counter 3 indicating the address at which the last read was performed, and found that the value of the write counter 2 was X + N +
When the value of the read counter 3 is X at 1, it is determined that the value is full,
The value of the write counter 2 is X and the value of the read counter 3 is also X
Is determined to be empty. These full and empty signals are used to control the next data input.

[0004]

However, in the above-mentioned conventional FIFO memory, when judging an empty state in which the values of the write counter 2 and the read counter 3 match, an erroneous signal called a hazard may occur. there were. This is because when the write address signal of the write counter 2 and the read address signal of the read counter 3 are compared by the AND circuit of the comparator 4, for example, as shown in FIG. 4, the write address signal and the read address signal change simultaneously. When a delay occurs in one of the read address signals, both the write address signal and the read address signal become high at the time of the delay, and the empty signal becomes high temporarily, which becomes a hazard. And convey incorrect information. Light counter 2
The write address signal from the read counter 3 and the read address signal from the read counter 3 do not cause a delay if the respective counters are completely the same, but in practice, they cannot be completely the same. Will happen.

An object of the present invention is to solve the conventional problems as described above, and an object of the present invention is to provide a hazard prevention circuit for a FIFO memory which can generate a full signal and an empty signal without causing a hazard. And

[0006]

According to the present invention, in order to achieve the above object, a flag is provided for each address of a FIFO memory, and when writing is performed at a certain address, a flag corresponding to the address is provided. Is set to "1", when reading is performed from the address, the flag corresponding to the address is set to "0", and the values of these flags are monitored to generate a full signal and an empty signal. is there. Thus, if all the flags are “1”, it is determined that the state is the full state, and if all the flags are “0”, it is possible to determine that the state is the empty state, and a full signal and an empty signal that do not generate a hazard are generated. be able to.

[0007]

According to the first aspect of the present invention, a flag is provided for each address of a FIFO memory, and when writing is performed on the address, the flag corresponding to the address is set to " 1), and when reading is performed from the address, a flag corresponding to the address is set to “0”, and an empty signal and a full signal are generated based on the value of each flag. When all the flags are "1", it is determined that the signal is in the full state, and when all the flags are "0", it is determined that the signal is in the empty state. Thus, a full signal and an empty signal that do not cause a hazard can be generated. .

According to a second aspect of the present invention, an FIF
A flag is provided in correspondence with each address of the O memory, and when writing to the address is performed, the flag corresponding to the address is set to “1”, and when reading from the address is performed, the flag corresponding to the address is set. Is set to “0”, and all outputs of the flags are ANDed.
A full signal and an empty signal are generated from their outputs, and if all the flags are "1", it is determined that the signals are in a full state. If “0” is “0”, it is possible to generate a full signal and an empty signal that do not cause a hazard by determining that the signal is in the empty state.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a data read / write control method according to the present embodiment. In FIG. 1, a write counter 12 and a read counter 13 are connected to a FIFO memory 11, and are controlled by a memory control unit (not shown). When writing data, the data is written to the address indicated by the write counter 12. In the FIFO memory 11, a data area 11a and a flag area 11b are provided at the same address. Now, when data 0 is written to the data area 11a at the address 0, "1" is written to the corresponding flag 0 in the flag area 11b. When data 1 is written to the data area 11a at the address 1, "1" is written to the corresponding flag 1 in the flag area 11b. Each time data is written, the value of the write counter 12 increases by one each time. When data N is written to the last address N, all flags are set to "1", and the FIFO memory 11 becomes full.

On the other hand, when reading data, the data is read from the address indicated by the read counter 13. Now, when the value of the read counter 13 is 0, the data 0 written at the address 0 is read,
The value of the flag 0 corresponding thereto becomes “0”. When the value of the read counter 13 is 1, the data 1 written at the address 1 is read, and the value of the flag 1 corresponding to the data 1 becomes “0”. Whenever the written data is read, the value of the read counter 13 increases by one each time. When the data N of the last address N is read, all the flags are set to "0", and the FIFO memory 11 is in the empty state. Becomes

The full state and the empty state of the FIFO memory 11 are determined by an AND circuit 14 and a NAND circuit 15.
Is determined by That is, in the full state, all the flags are “1”, and the AND circuit 14 that receives the outputs of all the flags outputs “1” and outputs a full signal. If any one flag is "0", "0" is output and no full signal is output. In the case of the empty state, all the flags are "0", so that the NAND circuit 15 which receives the outputs of all the flags outputs "1" and outputs the empty signal. If any one flag is "1", "0" is output,
No empty signal is output. At this time, for example, as shown in FIG. 2, after data 0 at address 0 is read and flag 0 becomes “0”, data 1 at address 1 is read and flag 1 changes to “0”. However, such a change is sequential, and two signals do not change at the same time as in the conventional example. Therefore, even if the AND circuit 14 or the NAND circuit 15 is used, a full signal or an empty signal is generated. Hazard does not occur.

As described above, according to the present embodiment, the FI
A flag is provided corresponding to each address of the FO memory 11, and when writing is performed at a certain address, the flag corresponding to the address is set to “1”, and when reading is performed from the address, the flag corresponding to the address is set. Is set to "0", and all outputs of each flag are input to the AND circuit 14 and the NAND circuit 15, respectively, to generate a full signal and an empty signal from those outputs. Can be prevented from occurring.

[0013]

According to the present invention, as is apparent from the above embodiment, a flag is provided for each address of the FIFO memory, and when writing is performed at a certain address, the flag corresponding to that address is set to " When reading is performed from the address, the flag corresponding to the address is set to "0", and a full signal and an empty signal are generated based on the values of these flags, so that no hazard occurs. A full signal and an empty signal can be generated.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a FIFO memory control method according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the embodiment of the present invention;

FIG. 3 is a schematic block diagram showing a FIFO memory control method in a conventional example.

FIG. 4 is a timing chart showing an operation in a conventional example.

[Explanation of symbols]

 Reference Signs List 11 FIFO memory 12 Write counter 13 Read counter 14 AND circuit 15 NAND circuit

Claims (2)

[Claims] 1. A flag is provided for each address of a FIFO memory, and when writing to the address is performed, the flag corresponding to the address is set to “1”, and when reading is performed from the address, the flag is set to “1”. A hazard prevention circuit for a FIFO memory, wherein a flag corresponding to an address is set to "0", and an empty signal and a full signal are generated based on the value of each flag. 2. A flag is provided corresponding to each address of the FIFO memory. When writing is performed on the address, the flag corresponding to the address is set to “1”, and when reading is performed from the address, the flag is set. A flag corresponding to an address is set to "0", all outputs of the flags are input to an AND circuit and a NAND circuit, respectively, and a full signal and an empty signal are generated from those outputs. Hazard prevention circuit.