JPS63196984A - Image data transfer circuit - Google Patents

Abstract

PURPOSE:To eliminate the restriction for transfer data length by enabling successively a decoder decoding a bus select data by a bus control signal, and storing successively an image data in an image memory. CONSTITUTION:When a horizontal direction picture element number (m) of image memories 14, 15, and a one horizontal direction picture element number (n) of an image data are in a relation of (m)<(n), a CPU 11 gives 3 and 2 to decoders 21, 22 as a bus select data BS1, and BS2, respectively. To a decoder selecting circuit 23, a bus control signal BS of an L level is applied, and the decoder 21 becomes enable. The decoder 21 decodes 3 and varies an output to an L level, and the image data is inputted to the memory 14. When the number of transfer data reaches (m), the CPU 11 makes the signal BC an H level, the decoder 22 is selected and the memory 15 is selected, and the image data extending from the (m)+1-th one to the (n)-th one are stored in the memory 15, therefore, an image processing of a wide application range can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image data transfer route for selectively transferring image data to a plurality of image memories via a plurality of buses.

(Prior Art) Conventionally, when selectively transferring image data to image memories connected to multiple buses, the buses are often controlled by bus select data from a CPU (central processing unit). . FIG. 5 shows an image data transfer circuit used in such a case. Bus select data BS from the CPUI is given to a decoder circuit 2 serving as a bus selection circuit. The decoder circuit 2 has bus enable signals A, B,
Output C and D. And this bus enable signal A
-D, the image data is transferred to the image memories 4, 5 . . . via the selector 3 and the selected bus. ...is selectively transferred to...

By the way, in such a system, conventionally, when data of one horizontal scanning line is transferred as one batch as image data, the number of data n that can be transferred in one data transfer is equal to the number of horizontal pixels in the image memory. If m, then m≧n
It was necessary to set the value within a range where the following relationship was established. this is,
When the number of transferred image data n exceeds the number m of horizontal pixels of the image memory, the transferred data exceeding the number m of horizontal pixels of the image memory must be stored in the next horizontal line of the image memory, and when reading the image This is because the address becomes complicated. Therefore, conventionally, there has been a problem in that the above-mentioned restriction on the number of image data transfers limits the scope of application of image processing.

(Problems to be Solved by the Invention) As described above, in the conventional image data transfer circuit,
There is a problem in that the number of data transferred at one time is limited in relation to the number of horizontal pixels of the image memory, which limits the scope of application of image processing.

The present invention is intended to solve such problems, and an object of the present invention is to provide an image data transfer circuit whose data transfer length is not affected by the size of an image memory.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a bus selection circuit that selectively enables one of a plurality of buses based on bus selection data, and a an image data transfer circuit that selectively transfers image data to the image memory connected to the bus through a bus selected by the bus selection circuit, the image data transfer circuit comprising an image memory connected to the bus selection circuit; , a plurality of decoders that respectively decode a plurality of the bus select data, and a decoder selection circuit that sequentially puts these decoders into an operable state based on a bus control signal during transfer of one image data.

(Operation) A plurality of decoders each decoding a plurality of bus select data are sequentially enabled during one data transfer based on a bus control signal, and each decoder sequentially selects a different bus. Therefore, during one data transfer, image data is sequentially stored in a plurality of image memories connected to these buses. Therefore, even if the number of transferred data exceeds the number of horizontal pixels of the image memory, the excess can be stored in a different image memory, so the length of the transferred data is not restricted to a specific length.

(Example) An example of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing the configuration of an image data transfer circuit according to this embodiment.

The CPU II sends two bus select data BSI, BS2 and a bus control signal B to the bus selection circuit 12.
C. The bus selection circuit 12 receives the bus selection data BSI, BS2 and the bus control signal B.
Based on C, two different bus enable signals A, B, C, and D are output to the selector 13 in one image transfer cycle. The selector 13 includes a bus Ba that transfers image data based on input bus enable signals A-D;
Select Bb, Bc, and Bd. Image data is transferred to image memories 14, 15, . . . via selected buses Ba-Bd.・・・
・Selectively stored in .

FIG. 2 is a diagram showing the bus selection circuit 12 in more detail. First bus select data BSI from CPUII
is input to the first decoder 21, and similarly, the second bus select data BS2 is input to the second decoder 22. Furthermore, the bus control signal BC is input to the decoder selection circuit 23. Decoder selection circuit B
Decoder enable signals DE1.C are used to sequentially select the decoders 21.22 based on the bus control signal BC. Output DE2. two decoders 21.2
2, the decoder output signal D11°D12. D13.
D14. D21. D22. D2B, D
Outputs 24. Decoder output signal D11. D21 is a signal for selecting the bus Ba, which is manually input to the NAND circuit 24 and output as the bus enable signal A. Decoder output signal D12. D 22ha/<X
To select B b (No. 2, NAND circuit 25
The bus enable signal B is input to the bus enable signal B and output as the bus enable signal B. Decoder output signal D13. D23 is a signal for selecting the bus Bc, which is input to the NAND circuit 26 and output as the bus enable signal C.

Furthermore, the decoder output signal D14. D24 is a signal for selecting the bus Bd, which is manually input to the NAND circuit 27 and output as a bus enable signal.

In the image data transfer circuit configured as above,
Now, assuming that the number of pixels in the horizontal direction of the image memory 14, 15 is m, and the number n of image data in one horizontal direction satisfies m<n, the following control is performed. C.P.U.I.
I gives, for example, "3" as the bus select data BSI and "2" as the bus select data BS2 to the decoders 21 and 22. Also, from the CPU II to the decoder selection circuit 23, as shown in FIG. Initially, the bus control signal BC at "L° level" is applied. As a result, the decoder selection circuit 23 outputs the decoder enable signal DEI to the decoder 21 to enable the decoder 21. The decoder 21 decodes the bus select data BSI "3" and changes the decoder output D14 from the "H" level to the 1L" level. As a result, the NAND circuit 27 outputs a bus enable signal, and the bus Bd Therefore, the image data is input to the image memory 14 via the selector 13 and the bus Bd.

On the other hand, the CPU II counts the number of transferred data from the start of image data transfer, and when the number of transferred data reaches m, changes the bus control signal BC from the "L" level to the "H" level as shown in Figure 3. . As a result, the decoder enable signal DE2 is output from the decoder selection circuit 23, and the decoder 22 is selected instead of the decoder 21. The decoder 22 decodes m2'' of the bus select data BS2 and outputs a decoded output D23. This decoder output D2 (is outputted as the bus enable signal C via the NAND circuit 26. As a result, the image memory 15
is selected, and the m+1st to nth image data are stored in the image memory 15.

Incidentally, the truth table of this bus selection circuit is shown in FIG.

In this way, according to this embodiment, even if the number n of image data to be transferred exceeds the number m of horizontal pixels of the image memory, the data portion corresponding to n-m is transferred to another image memory. can be stored in

Therefore, the number of image data to be transferred is not limited by the number of horizontal pixels of the image memory, as is the case in the past.

[Effects of the Invention] As described above, according to the present invention, the number of image data to be transferred is not restricted in relation to the image memory, and therefore it is applicable to a wide range of image processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image data transfer circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a bus selection circuit in the image data transfer circuit, and FIG. 3 is a block diagram showing the configuration of the image data transfer circuit. FIG. 4 is a timing chart for explaining the operation of the transfer circuit, FIG. 4 is a diagram showing the relationship between truth values, and FIG. 5 is a diagram showing the configuration of a conventional image data transfer circuit. 1.11...CPU, 2...Decoder circuit, 3゜13...Selector, 4.5.14.15...Image memory, 12...Bus selection circuit, 21.22... Decoder, 23...Decoder selection circuit, 24-27...
NAND circuit.

Claims (1)

[Scope of Claims] A bus selection circuit that selectively enables one of a plurality of buses based on bus selection data, and an image memory connected to each of the plurality of buses, the bus selection circuit comprising: In an image data transfer circuit that selectively transfers image data to an image memory connected to a bus selected by the circuit via a bus selected by the circuit, the bus selection circuit includes a plurality of buses that each decode the plurality of bus select data. 1. An image data transfer circuit comprising: a decoder; and a decoder selection circuit that sequentially puts these decoders into an operable state based on a bus control signal during transfer of one image data.