JP3357243B2 - Setting data changing device in image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a setting data changing device in an image processing device capable of changing setting data required for image processing, and more particularly to a setting suitable for image processing performed using a pipeline system. It relates to a data change device.

[0002]

2. Description of the Related Art At present, an image processing apparatus using a pipeline system is known as an effective image processing apparatus for processing continuously input image data. FIG. 5 is a diagram showing a schematic configuration of an image processing apparatus using the pipeline system. As shown in the figure, the pipeline system includes a plurality of stages ST1, ST2, ST3,... ST (N + M), and each of the stages performs predetermined processing on image data supplied via an image data bus B1. Image processing,
The data is sequentially transferred to the subsequent stage in accordance with each system clock CLK.

FIG. 6 is a block diagram showing a basic configuration of each stage of an image processing apparatus using a conventional pipeline system. As shown, each stage includes an image data latch circuit 1 for latching input image data by a system clock CLK, an image data processing circuit 2 for processing the image data, and an image data processing circuit 2. A register 3 and the like that store a selection signal for designating setting data such as a value required for processing in the processing circuit 2 and processing contents are provided. In such an image processing apparatus, the content of the image processing can be changed by changing the set value of the register 3. The change processing of the setting data in the register 3 is based on the data supplied from the CPU via the data bus B2 and the setting data stored in the register 3 which is the target of the register change instruction by the register selection signals S1 to SN. Change processing is to be performed.

[0004]

However, in the above-mentioned prior art, if the register 3 is updated while the image data is being processed in the pipeline, the image data is destroyed. Therefore, when the register 3 is updated, the image data existing in the pipeline includes all the stages ST1 constituting the pipeline.
~ ST ( N + M), then register 3 in the corresponding stage by the firmware.
Is updated. Therefore, every time the register 3 is updated, it is necessary to wait for the image data to pass through the pipeline, and the waiting time for the so-called pipeline flush in which the image data no longer exists in the pipeline. Required. Therefore, in the image processing in which the setting data of the register 3 is frequently changed, there is a problem that a sufficient drawing speed cannot be obtained due to a waiting time required for the pipeline flush.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and does not require a waiting time for a pipeline flush which has been indispensable for changing a register. An object of the present invention is to provide a setting data changing device of an image processing device capable of greatly reducing the processing time even in image processing in which setting data for setting is frequently changed.

[0006]

The present invention has the following arrangement to solve the above-mentioned problems. That is, claim 1 of the present application
According to the invention described above, setting data storing means for storing setting data for setting image processing contents, and performing image processing on image data input based on the setting data output from the setting data storing means. And an image processing unit for applying the setting data, wherein the setting data storage means is configured to form a multiplex structure by a plurality of registers storing a plurality of different setting data, and is synchronized with the image data. Selection signal transmitting means for outputting a selection signal for selecting a register storing setting data corresponding to required image processing, and selecting the plurality of registers based on a selection signal transmitted from the selection signal transmitting means And selection means for performing the selection. According to a second aspect of the present invention, the selection signal transmitting means is constituted by image data and an image memory device for storing a selection signal corresponding to the image data.

Further, according to a third aspect of the present invention, there is provided a setting data storing means for storing setting data for setting image processing contents, and an input based on the setting data outputted from the setting data storing means. In a pipeline-type image processing apparatus in which an image processing stage including an image processing unit that performs image processing on image data is set in multiple stages, the setting data storage unit stores a plurality of different setting data. A selection signal output means for outputting a selection signal indicating a processing stage and a register corresponding to required image processing, in synchronization with image data, and output from the selection signal output means. And selecting means for selecting a predetermined stage and a register from the plurality of registers based on the selected selection signal. You have me. Further, according to a fourth aspect of the present invention, the selection signal output means according to the third aspect further comprises:
It is configured by an image memory device that stores image data, a processing stage and a selection signal corresponding to the image data.

According to the first or second aspect of the present invention, setting data having different contents for setting image processing contents are stored in a plurality of registers having a multiplex structure, respectively. Select the processing content to be performed by the processing unit. The choice of this register is
Since the image processing required by the selection means is selected based on a signal generated from the selection signal output means in synchronization with the image data, continuously input image data can be processed appropriately and quickly.

According to the third or fourth aspect of the present invention, in the image processing apparatus using the pipeline system, when changing the image processing content in each stage, the image processing is output in synchronization with the image data. In order to perform pipeline processing while selecting and executing a predetermined image processing as appropriate by selecting a processing stage and a register in which a selection signal should change processing content, as in the related art, in changing image processing content, The image processing content can be changed without waiting for a pipeline flush in which image data does not exist from within the pipeline, and image processing that is continuously input can be efficiently executed. Therefore, high-speed drawing can be performed even in computer graphics in which setting data related to image processing is frequently changed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus using a pipeline processing method applied to an embodiment of the present invention, and FIG. 2 is a diagram showing setting data change in each stage of the image processing apparatus shown in FIG. FIG. 3 is a block diagram showing a configuration of the apparatus, FIG. 3 is an explanatory diagram showing a data configuration of an image memory device used in the embodiment, and FIG. 4 is a timing chart showing an operation in the embodiment.

As shown in FIG. 1, also in the pipeline processing system applied to the embodiment of the present invention, a plurality of image processing stages ST1 to ST (N + M) are used, similarly to the pipeline processing system shown in the above-mentioned prior art. ) And image data D transferred by the image data bus 100.
1 in each stage S in sequence by the system clock CLK.
The data is transferred to T1 to ST (N + M), and predetermined image processing is performed in each stage. This point is the same as that shown in the above-mentioned prior art, but each stage ST1 to ST (N + M) is processed. ST (N + M) configuration and each stage ST1
Data and signals input to .about.ST (N + M) are different as shown in FIG. Hereinafter, this embodiment will be described in detail with reference to FIG.

The stage shown in FIG. 2 shows an M-th stage ST (N + M) in the pipeline. In the figure, reference numeral 101 denotes an image for latching image data D1 inputted via an image data bus 100. A data latch circuit 102 is an image data processing circuit (image processing unit) that performs image processing on image data output from the latch circuit 101 in accordance with setting data from a register described later.
It is. To the latch circuit 101, data (stage number data) D2 designating the number of stages for which the image processing content needs to be changed is input via the data bus 103, and register switching for instructing switching timing of a plurality of registers is performed. Signal RCE and system clock CLK are input via signal lines 104 and 105, respectively.

Further, two comparators 106 and 107 are provided at the subsequent stage of the image data latch circuit 101. Data “0” is stored in one of the comparators 106.
And data D2 representing a stage value (a stage value requiring a change in image processing) outputted from the latch circuit 101, and the other comparator 107
Also includes data D2 output from the latch circuit 101.
And the stage value of the actual stage (here, the stage number (M)).

Further, an OR gate 108 for outputting a logical sum of respective outputs is connected to the comparators 106 and 107, and an output signal thereof is input to one input terminal of an AND gate 109. . The other input terminal of the AND gate 109 is connected to the latch circuit 101.
The output of the register switching signal RCE is input, and the AND gate 109 outputs the logical product of the two signals to the CE terminal (clock enable input terminal) of the counter 115 provided at the subsequent stage. The system clock CLK is input to the counter 105. When a predetermined input (here, “1”) is input to the CE terminal, the counter 105 counts the system clock CLK, and responds to the count value. Output terminals (0), (1),
One of (2) and (3) is activated (outputs selection signals S1, S2, S3, S4). In addition, 106, 10
7, 108, 109 and 115 constitute the selecting means 10 according to the present invention.

On the other hand, reference numerals 116, 117, 118, and 119 denote four registers for storing values representing the functions and constants for the image processing. Values representing different processing contents are stored in these registers. The register constitutes a storage means 20 having a quadruple structure. A CPU data bus 110 for writing data to the registers by firmware is connected to each data input terminal DI of each of the registers 116, 117, 118, and 119, and is connected to each of the registers 116, 117, 118, and 119. The data output terminal DO is connected to the image data processing device 102 via the register bus 120. Further, register write signals W1, W2, W3, and W4 can be input to the write terminals WR of the registers 116, 117, 118, and 119 via signal lines 111, 112, 113, and 114, respectively.

FIG. 3 shows a data structure of the image memory device 200 used in this embodiment. As shown in the figure, in the image memory device 200, each image data D1 sequentially sent to the pipeline, and a register switching signal RCE and stage number data D2 corresponding to each image signal are stored in areas corresponding to each other. At the same time, the reading is performed in synchronization with the data in the corresponding area, and constitutes the selection signal output means of the present invention.

In FIG. 3, (N-1) to (N + 4) described in the image data indicate the order of reading to the pipeline. The register switching signal RCE shown here is a 1-bit signal represented by "1" or "0", and "1" means that switching is performed. Further, in the stage number data D2, M and P represent the number of stages to be switched, and 0 means switching in all stages. Therefore, (N) shown here
The register switching of the (N + 2) th image data is performed in the processing of the P-th stage STP, and the register switching is performed in the processing of the M-th stage STM. The ()) th image data indicates that setting data is switched in all stages.

The registers 116, 117, 11
8 and 119 are stored in the image memory 200.
Is set in advance by using the register write signals W1, W2, W3, and W4 in accordance with the contents stored in the register. For example, the register value for the image data (N-1) is (0-1), the register value for the image data (N) is (0), and the register value for the image data (N + 1) is (0 + 1). Assuming that these values are required by the image data processing circuit 102, (0-1) is stored in the register 116, (0) is stored in the register 117, and the register 11
In (8), (0 + 1) is set in advance.

Next, the operation based on the above configuration will be described. Image data D1 read from image memory 200
Are transferred to the first stage ST1 of the pipeline via the image data bus 100, and then sequentially transferred to the subsequent stages according to the timing of the system clock CLK. Now, assuming that the N-th image data is transferred to the M-stage STM, the stage number data D2 and the register switching signal RCE are synchronized with the image data D1.
Are transferred to the M-stage STM. Then, the image data transferred to the stage STM is
After being latched at 01, it is input to the image data processing circuit 102, and the stage number data D2 is input to the comparators 106 and 107, respectively.

The register switching signal REC is input from the latch circuit 101 to the AND gate 109. Here, the comparator 106 calculates the stage value represented by the inputted stage number data D2 and the stage value (M) in the current stage.
The comparator 107 outputs an output signal “1” if the values match, and outputs “0” if they do not match. In this case, the stage number data D2 is as shown in FIG.
Since the value is M as shown in (2), the two data values input to the comparator 107 match, and the comparator 107 outputs “1”. As a result, the output from the OR gate 108 becomes “1”, which is input to one input terminal of the AND gate 109.

The other input terminal of the AND gate 109 receives a register switching signal RCE. Here, as shown in FIG. 4, the RCE signal is "1".
Therefore, the output signal of the AND gate 109 is 1
Becomes Since the output signal “1” of the AND gate 109 is input to the clock input permission terminal CE of the counter 115, the counter 115 receives the system clock CLK. Therefore, the counter 115 counts up by one, and the output terminals (0), (1), (2), (3)
Is selectively activated.

Here, the output terminal (1) of the counter 115
Becomes active, the data output enable input terminal OE of the register 117 connected to this output terminal.
Becomes active, and the data set in the register 117 is transferred to the image data processing circuit 1 via the register bus D3.
02. The image processing data circuit 102 performs predetermined image processing on the input image data according to the setting data of the register 117.

Thereafter, when the next system clock is input, the processed image data is sent to the next station, and the (N + 1) -th image data is stored in the image data latch circuit 101 of this station ST1. Data D
1 is transferred. In addition to the image data D1, the register switching signal RCE and the stage number data D2 are also stored in the latch circuit 1.
01 is input.

The stage number data D2 is "0" as shown in FIG. 3, and the value of "0" is the register value for all stages if the value of the register switching signal RCE is "1". Switching is performed. That is, the value “0” is input to both input terminals of the comparator 106.
And a preset value 0 are input together, and “1” is output from the comparator 106 and the OR gate 10
8 outputs “1”. The register switching signal R
Since CE is 1 as shown in FIG.
09 is input to both input terminals, and “1” is output from the output terminal.
E becomes active. For this reason, the counter 115 counts up by one according to the system clock CLK, the active output terminal of the counter 115 is switched, and the register from which the setting data is read is switched. Here, the counter 11 is used in the previous image processing.
Since the output terminal (1) of the counter 115 is active, the output terminal (2) of the counter 115 becomes active by the current count-up. Thereby, the register 11
8 are sent to the image data processing circuit 102 via the register bus D3, and image processing is performed according to the set data contents.

Thereafter, according to the system clock CLK, the stage number data D2 together with the (N + 2) th image data D1
When the register switching signal RCE is input, the preset value “0” and the stage number data “P” are input to the comparator 106, so that the output is “0”. Also in the above, since the stage number data “P” is compared with the preset stage number “M”,
The output is "0". Therefore, "0" is output from the OR gate 108, and the output signal "0" from the OR gate 108 and the register switching signal "1" are input to the AND gate 109, so that the output is "0". Become. As a result, the input terminal CE of the counter 115 becomes inactive, the count operation for the system clock CLK is not performed, and the count value up to that time is maintained. That is, since the output terminal (2) of the counter 115 is kept active, the image data processing circuit 1
The setting data input to 02 is not changed, and the same image processing as before is performed.

[0026]

As described above, according to the setting data changing apparatus in the image processing apparatus according to the present invention, the selection of the setting data for setting the contents of the image processing is performed by the selection signal output in synchronization with the image data. In the image processing in which the setting data is frequently changed, the image data can be sequentially and continuously processed.
Processing time can be reduced. In particular, in an image processing apparatus using a pipeline system, if a selection of a processing stage and a register that require a change in processing content is performed by a selection signal output in synchronization with image data, the input image data On the other hand, required image processing can be executed at any time. Therefore, when setting data is changed, the waiting time for pipeline flush, which has been indispensable in the conventional apparatus, can be reduced, and the processing time can be significantly reduced.
High-speed drawing can be realized even in computer graphics in which setting data is frequently changed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image processing apparatus using a pipeline processing method applied to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a setting data changing device in each stage of the image processing device shown in FIG.

FIG. 3 is an explanatory diagram showing a data configuration of an image memory device used in the embodiment.

FIG. 4 is a timing chart showing an operation in the embodiment.

FIG. 5 is a diagram illustrating a schematic configuration of an image processing apparatus using a conventional pipeline method.

FIG. 6 is a block diagram showing a basic configuration of each stage in an image processing apparatus using a conventional pipeline system.

[Explanation of symbols]

 102 Image processing circuit (image processing unit) 10 Selection means 20 Storage means 116, 117, 118, 119 Register 200 Image memory (selection signal output means) ST1-ST (N + M) Processing stage

Claims (4)

(57) [Claims] A setting data storage unit configured to store setting data for setting image processing contents; and performing image processing on image data input based on the setting data output from the setting data storage unit. The setting data storage means is configured to form a multiplexed structure by a plurality of registers storing a plurality of different setting data, and is synchronized with the image data. Selection signal output means for outputting a selection signal for selecting a register storing setting data corresponding to image processing to be performed, and selection for selecting the plurality of registers based on a selection signal output from the selection signal output means. And a setting data changing device in the image processing device. 2. The setting data changing device according to claim 1, wherein said selection signal output means is an image memory device for storing image data and a selection signal corresponding to the image data. 3. A setting data storing means for storing setting data for setting image processing contents, and performing image processing on image data inputted based on the setting data outputted from the setting data storing means. In a pipeline-type image processing apparatus in which stages including an image processing unit to be applied are set in multiple stages, the setting data storage unit may have a multiplex structure by a plurality of registers storing a plurality of different setting data. A selection signal output unit configured to output a selection signal indicating a stage and a register corresponding to required image processing in synchronization with image data, and a plurality of the selection signals output from the selection signal output unit. And a selecting means for selecting a predetermined stage and a register from the registers. Setting data changing device that. 4. The setting in the image processing apparatus according to claim 2, wherein the selection signal output means is an image memory device for storing image data, stage number data and a selection signal corresponding to the image data. Data change device.