JP2579696B2 - Buffer control device - Google Patents

Description

The present invention relates to a buffer control device for processing untransferred data remaining in a data shift type buffer having a data width conversion function, and simplifies an operation for extracting untransferred data from a buffer by a processor. The purpose of this is to prevent inadvertent destruction of the SS, and when a transfer end instruction is received, the position in the buffer of the remaining data that has not been transferred in the buffer is 2N bits of the final stage buffer. A register with a function to indicate the N-bit area of the first-stage buffer is provided, and the processor knows the buffer position where untransferred data remains from the register contents, reads the untransferred data directly, and transfers it to SS etc. Configure.

[Industrial Application Field] The present invention relates to an apparatus for processing untransferred data remaining in a data shift type buffer.

In recent years, with the demand for high-speed computer systems, a data buffer is often used in a channel section in order to improve a data transfer rate.

In particular, when the buses of the interfaces located at both ends of the buffer of the channel section are different, a data shift type buffer which also serves to convert the data width is used. However, in such a data shift type buffer that also converts the data width, if the transfer data does not become an integral multiple of the transfer unit number of the transfer destination interface, the data remains in the buffer at the end of the transfer. . Therefore, a process for efficiently extracting the untransferred data remaining in the buffer and sending it to a required location is desired.

[Prior Art] FIG. 5 shows a conventional data shift type buffer that also performs data width conversion.

In FIG. 5, reference numeral 10 denotes a data shift type buffer. In this case, the buffer is composed of 2N bits and M = 4 stages. An interface 14 is provided on the left side of the data shift buffer 10, and the interface 14 has a data bus 22 having an N-bit width, and can transfer N-bit data by one transfer. An interface 12 is provided on the right side of the data shift buffer 10, and the interface 12
Data can be transferred in units of 4N bits in one transfer on the data bus 20 having a width of 2N bits, and 2N bits of data can be transferred at the time of final transfer.

For example, when data is transferred from the interface 14 to the interface 12 as shown in the figure, the data shift buffer 10 accumulates data in the first-stage buffer 10-1 and aligns the data with the bus width of 2N bits of the transfer destination interface 12. Then, after confirming that the buffer 10-2 of the next stage is empty, the shift is performed, and the buffer is shifted one after another to the buffer 10-4 of the last stage. Then, when the 4N-bit data serving as the transfer unit of the transfer destination interface 12 has been prepared in the final stage and the buffers 10-4 and 10-3 at the preceding stage, the transfer request is raised and the transfer is started. . When the required number of data has been transferred, a transfer end instruction is issued to terminate the transfer.

[Problems to be Solved by the Invention] By the way, in the conventional data shift type buffer control device, the transfer ends in a normal transfer in which the number of transfer data is an integral multiple of the number of transfer units of the transfer destination interface. Untransferred data does not remain in the buffer when this is done. However, for example, when the transfer unit of the transfer destination interface 12 is 4 bytes and the transfer interface of the transfer destination interface 14 is 1 byte, if 4N + 3 bytes are transferred, only 4N bytes which is an integral multiple of the transfer unit are normal. The remaining three bytes may be left in the data shift buffer 10 after being transferred to the transfer destination interface.

Therefore, control for transferring the untransferred data accumulated in the buffer and terminating the transfer is required. For this reason, one byte of dummy data that is insufficient to control the transfer source interface 14 is fetched into the buffer, and 4-byte data, which is the transfer unit of the transfer destination interface, is aligned and sent to the interface 14.

However, the control of the interface 14 at this time is generally performed by the intervention of a processor, which requires many operations, and has a problem that the load on the processor increases and the transfer time increases.

In addition, in the case of an operation of storing transfer data in the system storage (SS), there is also a problem that data in the system storage may be destroyed by dummy data.

The present invention has been made in view of such a conventional problem, and has been made of a data shift type buffer which simplifies an operation of extracting untransferred data from a buffer by a processor and prevents inadvertent destruction of SS. It is an object to provide a buffer control device.

Means for Solving the Problems In order to achieve such an object, the present invention has a storage capacity of a plurality of levels with a predetermined capacity, and when data of a predetermined capacity is prepared in the storage area of each level, the storage of the next level is performed. Data holding means for shifting data to the area (data shift type buffer
10-1 to 10-M); means (first interface 12) connected to the output end of the data holding means for transferring the data of the plurality of storage areas in the first floor transfer; Means for instructing a storage area in which data remaining without being transferred in the data holding means when receiving the instruction (the buffer control unit 24, the register 18-
2) and means (processor 16) for reading data in the storage area corresponding to the untransferred data position based on the instruction.

Further, the present invention has a plurality of storage areas with a predetermined capacity,
A data holding means (data shift type buffers 10-1 to 10-M) for shifting data to a storage area of the next stage when data of a predetermined capacity is arranged in a storage area of each stage; A means (second interface 14) for transferring data of each division unit obtained by equally dividing the storage area in one transfer, and transferring the data to the data holding means when receiving a data transfer end instruction. Means for specifying the storage area where the remaining data is stored (buffer control unit 24, register 18-
1) and means (processor 16) for reading data in a storage area corresponding to the untransferred data position based on the instruction.

[Operation] FIG. 1 is a principle view of the present invention.

First, the present invention is directed to a buffer control device for a data shift type buffer having the following configuration.

That is, a data bus having a 2N bit width is provided at both ends of the data shift buffer 10 having a storage area of 2N bits and M stages.
20 has a first interface 12 capable of transferring data of 4N bits in a single transfer or 2N bits in the last transfer, and a data bus 22 having an N-bit width, enabling data transfer in an N-bit unit by one transfer. Two data transfer interfaces of the second interface 14 are provided.

The data shift buffer 10 shifts data to the next area in the same direction whenever 2N-bit data is stored in the buffer.

In the first interface 12, a data shift buffer
At the time of the operation of storing data in 10, if there is an empty 4N bit data area in the first stage and the next stage, a transfer request signal is sent out,
Conversely, it has a function of transmitting a transfer request signal when 4N-bit transfer data is present in the last stage and the preceding stage during the operation of discharging data from the data shift buffer 10.

The second interface 14 transmits a transfer response signal in response to a transfer request signal if an N-bit data area is empty at the first stage during the operation of storing data in the data type buffer 10, and conversely, the data shift type buffer 10 It has a function of transmitting a response signal in response to a transfer request signal when N-bit transfer data is present at the last stage during an operation of discharging data from the device.

In such a buffer control device, in the present invention, when a transfer end instruction is received, the 2N of the final stage 10-M is determined as the position in the buffer of the data remaining untransferred in the data shift buffer 10. Registers 18-1 and 18-2 that can be read from the processor 16 having a function of indicating the bit amount and the N-bit area of the first stage 10-1 are provided.
The position of the untransferred data in the buffer can be immediately recognized by the processor 16 from the contents of 18-2.

Further, a configuration is adopted in which the data in the buffer areas 10-1 and 10-M corresponding to the untransferred data positions indicated by the registers 18-1 and 18-2 are connected to the processor 16 so as to be directly readable.

According to the buffer control device of the present invention having such a configuration, the following operation can be obtained.

In FIG. 1, at the time of transfer from the second interface 14 to the first interface 12, N-bit data is fetched from the second interface 14 in the order of the buffer areas H and L of the first-stage buffer 10-1. The buffers 10-2, 10-3, 10-4 are shifted by the control signal of the unit 24,
When 4N bits of data are prepared in the final stage 10-4 and the preceding stage 10-3, the data is transferred to the first interface 12.

When receiving the end notification, the buffer control unit 24 checks the empty state of the first stage 10-1 and the last stage 10-M of the data shift type buffer 10, and if any untransferred data remains, the corresponding registers 18-1 and 18-2. Set the bits of Register 18-1,
18-2 has a bit indicating the position of the untransferred data in the buffer. By reading this bit from the processor 16, the position of the untransferred data in the buffer can be determined. Therefore, the processor 16 performs a process of untransferred data in which data of each buffer corresponding to the bits of the registers 18-1 and 18-2 is read and written to a storage area such as a storage device (SS).

[Embodiment] Fig. 2 is an embodiment configuration diagram showing one embodiment of the present invention.

In FIG. 2, interfaces 12 and 14 are provided at both ends of a data shift type buffer 10, and in this embodiment, the interface 12 is a transfer destination interface.
The interface 14 is the transfer source interface. The bus width of the data bus 20 of the transfer destination interface 12 is 2 bytes (16 bits), the bus width of the data bus 22 of the transfer source interface 14 is 1 byte (8 bits). The unit is 4 bytes, and the transfer unit of the transfer source interface 14 is 1 byte.

The data shift type buffer 10 includes a first-stage buffer 10-1, a second-stage buffer 10-2, and a third-stage buffer 10- for transferring data from the interface 14 to the interface 12.
3. It has a four-stage configuration of the last stage buffer 10-4. On the other hand, for data transfer from the interface 12 to the interface 14, the first-stage buffer 10-5 and the second-stage buffer 10-
The second-stage buffer 10-3 and the last-stage buffer 10-6 have the same four-stage configuration. The first-stage buffers 10-1 and 10-5 in each transfer direction are connected to the second-stage buffers 10-1 and 10-5 through the selector 26.
-2. The output of the third-stage buffer 10-3 is supplied in parallel to the last-stage buffers 10-4 and 10-6 in each transfer direction. Therefore, in the data shift type buffer 10, the first stage buffer 10-1 or 10-5, the second stage buffer 10-2, the third stage buffer 10-3, and the last stage buffer 10-3.
It is assumed that data is always shifted in the order of 10-4 or 10-6.

Further, the storage data width of each of the buffers 10-1 to 10-6 provided in the data shift type buffer 10 is 2 bytes, and buffers for input / output with respect to the interfaces 12 and 14, that is, the first stage buffers 10-1 and 10-6. -5 and last buffer
For 10-4 and 10-6, 1 byte in the youngest transfer order is 2 bytes.
The data is stored in the upper area H of the byte buffer area, and the lower area L of the remaining 1 byte is used as a data storage area in the next transfer order.

When data is transferred from the interface 12 to the interface 14 in such a data shift type buffer 10, the first two bytes are first transferred to the first-stage buffer 10-5 when data is read in units of 4 bytes from the interface 12. Take in. Next, the data in the first-stage buffer 10-5 is passed through the multiplexer 26 to the second-stage buffer 10-5.
2 and the next 2 bytes
The operation of taking in -5 is performed. In the same manner, shifting is performed one after another while checking the empty state of the buffer at the next stage. When the data arrives at the final buffer 10-6, the data is sent to the interface 14 by one byte in the order of the upper area H and the lower area L. When the transfer of all data is finally confirmed, the transfer is terminated by a transfer end notification.

Conversely, when data is transferred from the interface 14 to the interface 12, the data is fetched from the interface 14 one byte at a time in the order of the upper region H and the lower region L of the first-stage buffer 10-1, and two bytes are transferred to the first-stage buffer 10-1. When the data for the byte is completed, the data is shifted to the second buffer 10-2 via the multiplexer 26. The data shifted to the second-stage buffer 10-2 is sequentially shifted to the third-stage buffer 10-3 and the final-stage buffer 10-4.
When the data of 4 bytes are available in the third buffer 10-3 of the preceding stage and the third stage buffer 10-3, the data is transferred to the interface 12. Finally, when the transfer of all data is confirmed, the transfer is terminated by a transfer end notification. In the data transfer from the interface 14 to the interface 12, for example, as shown in the upper area H of the first-stage buffer 10-1, when 1-byte data is stored, the shift to the second-stage buffer 10-2 is not performed. The shift to the second and subsequent stages is performed after waiting for the data of the next lower region L. That is, the data shifted from the first-stage buffer 10-1 is shifted one after another without being held in the middle buffer, and packed to the last stage, and the intermediate stage is always kept empty for the next data shift. become.

Here, when converting 1-byte data coming from the interface 14 to 2-byte data and transferring it to the interface 12, the number of data to be transferred at the interface 12 is 4N bytes and the number of data actually transferred at the interface 14 is
Assuming that 4N + 3 bytes, 4N bytes of data are transferred to the interface 12 via the data shift buffer 10.
When the transfer of 4N bytes is completed, the interface 12 notifies the end of the transfer and terminates the data transfer. However, when the interface 12 terminates the data transfer, the remaining three bytes of data remain in the data shift type buffer 10 at this time. More specifically, data remains in the upper region H of the first-stage buffer 10-1 and the upper and lower regions H and L of the last-stage buffer 10-4, as indicated by hatched portions. The reason why untransferred data remains in the data shift type buffer 10 is that the number of data from the interface 14 is 4N + 2 bytes and 4N + 4 bytes in addition to 4N + 3 bytes.
This also occurs in the case of one byte. In the case of 4N + 2 bytes, untransferred data remains in the last stage buffer 10-4, and 4N + 1
In the case of bytes, untransferred data remains in the upper area H of the first stage buffer 10-1.

In order to detect the position of the untransferred data remaining in the data shift type buffer 10 at the end of the data transfer, the registers 18-1 and 18-2 are provided in the present invention. The register 18-1 is provided corresponding to the first-stage buffer 10-1, and the register 18-2 is provided corresponding to the last-stage buffer 10-4. When receiving the transfer end instruction signal, the registers 18-1 and 18-2 store a flag F1 of the first stage buffer 10-1 and a flag F2 of the last stage buffer 10-4 indicating that untransferred data remains. Based bit set is performed.

The registers 18-1 and 18-2 are connected to the processor 16 via the multiplexer 30, and when the registers 16-1 and 18-2 are read from the processor 16, the untransferred data remaining in the data shift buffer 10 is read. The position of the data can be known. Furthermore, for the processor 16, the first-stage buffer 10-
1 upper region H and the upper region of the last stage buffer 10-4
H and the lower area L are connected via a multiplexer 30 so as to be read-accessible. Because of this, the processor
16 indicates the transfer data required by reading the contents of the corresponding buffers 10-1 and 10-4, if the position of the untransferred data in the buffer remains by reading the registers 18-1 and 18-2. All, for example, system storage 32
And a series of transfer operations can be terminated.

A buffer control unit is provided below the data shift type buffer 10.
24 is shown. The buffer control unit 24 generates a sampling clock for data shift for the interface control circuit 34 for the interface 12, the interface control circuit 36 for the interface 14, and the buffers 10-1 to 10-6 of the data shift type buffer 10. A sampling clock generating circuit 38, a buffer full signal generating circuit 40 for generating a buffer full signal in accordance with a data shift of each of the buffers 10-1 to 10-6 of the data shift type buffer 10, and a data transfer from the interface 14 to the interface 12. Is performed, a non-transferred data detection unit 50 is provided which detects which position of the first-stage buffer 10-1 and the last-stage buffer 10-4 has untransferred data when receiving a transfer end instruction signal.

For such a buffer control unit 24, first, a data shift type buffer by a sampling clock generation circuit 38
The data shift operation in 10 will be described as follows.

FIG. 3 is a data shift type buffer for data transfer from the interface 14 to the interface 12 in FIG.
The configuration of FIG. 10 is shown in a simplified manner, for example, a case where the configuration is constituted by three stages of buffers 10-1, 10-2, and 10-3.

Note that the buffer 10-1 stores 1
The byte area is defined as a buffer 10-1H (showing the high side) and the other is defined as a buffer 10-1L (showing the low side).

Each of the buffers 10-1 to 10-3 having a three-stage configuration is supplied with a sampling clock from the sampling clock generation circuit 38 in FIG. Specifically, the sampling clock generation circuit 38 starts generating a sampling clock in response to a sampling trigger signal from the interface control circuit 36 of the interface 14 as the transfer source. Since the interface 14 transfers data in units of one byte, the buffer 10
Separate sampling clocks are provided for -1H and 10-1L.

FIG. 4 is a timing chart showing a data shift operation in the buffers 10-1 to 10-3 of FIG. 3, and also shows an operation of detecting untransferred data after receiving a data transfer end instruction. .

In FIG. 4, T1, T2, T3... Represent one cycle of the operation clock, and buffers 10-1 to 10-
In FIG. 3, a black circle indicates a signal on state, and a white circle indicates a signal off state.

In the following description, it is assumed that the total transfer data permitted by the interface 12 is 4N bytes, while the total transfer data transmitted from the interface 14 is 4N + 2 bytes.

First, in the first T1 cycle, data transfer of 4 (N-1) bytes has already been completed, and the buffer 10-
It is assumed that five bytes of data are stored in the buffer 10, two bytes each in the third and second stage buffers 10-2 and one byte in the buffer 10-1. And the interface
It is assumed that a data transfer request signal has been transmitted to Twelve.

In this state, in the next T2 cycle, 1-byte data is read from the interface 14 into the buffer 10-1L by the sampling clock of the buffer 10-1L. In the next T2 cycle, a transfer timing signal is asserted from the interface 12 to transfer 2 bytes of data from the buffer 10-3 and to turn off the buffer full signal of the buffer 10-3. At the same time, it can be predicted that the buffer 10-3 will be empty in the next T4 cycle.
3 is asserted and the buffer 10-3 is asserted.
Of the buffer 10-2.

When the data of the buffer 10-2 is taken into the buffer 10-3, the buffer full signal of the buffer 10-2 at the preceding stage is turned off, and at the same time, the buffer full signal of the buffer 10-3 is turned on. In this case, the operation of turning on the buffer full signal of the buffer 10-3 has priority.

In the next T4 cycle, data shift from the buffer 10-1 to the buffer 10-2 and 2-byte data transfer from the buffer 10-3 to the interface 12 are performed. First, the data shift from the buffer 10-1 to the buffer 10-2 is generated on condition that the buffer full signal of the buffer 10-1 is on and the buffer full signal of the buffer 10-2 is off. When the data from the buffer 10-1 is shifted to 10-2, the buffer full signal of the buffer 10-1 is turned off, and at the same time, the buffer full signal of the buffer 10-2 is turned on.

On the other hand, the buffer 10-3 transfers 2 bytes of data in accordance with the transfer timing signal from the interface 12, thereby completing the transfer of a total of 4N bytes.
When the data transmission from the buffer 10-3 is completed, the buffer full signal of the buffer 10-3 is turned off.

In the next T5 cycle, data shift from the buffer 10-2 to the buffer 10-3 is performed. That is, when the buffer full signal of the buffer 10-2 is on and the buffer
The sampling clock is supplied to the buffer 10-3 on condition that the buffer full signal of the buffer 10-3 is off, and the data of the buffer 10-2 is shifted to the buffer 10-3. When the shift to buffer 10-3 is completed, buffer 10-
2 to turn off the buffer full signal, and
Turn on the buffer full signal of.

In this state, the interface 12 which has completed the data transfer of 4N bytes in the T4 cycle does not transmit data from the next buffer 10-3 even if it waits for a predetermined number of cycles or more. Put out. At this time, the untransferred data shifted in the T5 cycle remains in the buffer 10-3 at the last stage, so that the next Tn
Register setting indicating remaining data is performed in +1 cycle.

Referring to FIG. 2 again, the untransferred data detection unit 50 provided in the buffer control unit 24 includes a first stage obtained from the buffer full signal generation circuit 40 in accordance with the buffer data shift as shown in the time chart of FIG. Based on the buffer full signals of the buffer 10-1 and the final stage buffer 10-4, when a transfer end instruction signal is obtained, a register set flag indicating the position of the untransferred data is generated. That is, the untransferred data detection unit 50 is provided with the FF42 for the first-stage buffer 10-1 and the FF44 for the last-stage buffer. The buffer full signal generation circuit 40 supplies the buffer full signal BF1 of the first buffer 10-1 to the J terminal of the FF42, and the buffer full signal BF4 of the final buffer 10-4 to the J terminal of the FF44. FF42,44 are connected to the terminal when the system starts up,
A clear logic is given at the start of transfer or the like. Also, FF42,4
A transfer end instruction signal from the interface 12 side is given to the ▲ ▼ terminal of 4 from the AND gate 46 in synchronization with the system clock, and the FFs 42 and 44 are set / cleared by the clock generated by the transfer end instruction signal. And
At this time, the bit state of the buffer full signals FB1 and FB2 received from the buffer full signal generation circuit 40 is fetched, and the corresponding flag outputs F1 and F2 are set in the shift registers 18-1 and 18-2 via the multiplexer 48. Like that.

As described above, since the present invention transfers 4N bytes of data over a 2N bytes bus, the present invention transfers the data in two steps, which is compared with the case of transferring 4N bytes of data over a 4N byte bus. And the configuration becomes complicated. This slightly increases the number of circuits, which can be covered by the LSI element layout and wiring. However, compared to those that transfer 4N bytes of data on a 2N byte bus, those that transfer 4N bytes of data on a 4N byte bus increase the number of pins, and the increase in the number of pins directly leads to a change in the package, This leads to higher costs. That is, a recent LSI can be configured more economically than a method of increasing the number of pins even if the circuit becomes slightly complicated.

In the untransferred data detecting section 50 shown in the embodiment of FIG. 2, if there is untransferred data in the first stage buffer 10-1 and the last stage buffer 10-4, the flag is set to 1 and the register 18- Bits 1 are stored in 1, 18-2, but untransferred data remains in both the upper region H and the lower region L in the final stage buffer 10-4, and untransferred data remains only in the upper region H. Since the buffer full signal may be
Expressed in bits, and similarly, the register 18-2 of the final-stage buffer 10-4 is expressed in two bits, so that there is untransferred data in both the upper and lower parts of the final-stage buffer 10-4 to the processor 16. It is desirable to be able to notify whether or not there is untransferred data only in the upper area. Also,
In the above embodiment, the bus width of the transfer destination interface 12 is 2 bytes, and the bus width of the transfer source interface 14 is 1 byte.
Although described as bytes, the present invention is not limited to this,
The same applies to data transfer between appropriate interfaces in which the bus width of the transfer destination interface 12 is 2N bits and the bus width of the transfer source interface 14 is N bits. This is the same for the transfer in the reverse direction from the interface 12 to the interface 14.

[Effects of the Invention] As described above, according to the present invention, in the control of the data shift type buffer having the data width conversion function, even if untransferred data remains in the buffer at the end of data transfer, dummy data The transfer can be terminated by reading the register indicating the untransferred position in the buffer from the processor without transferring the data, and then directly reading and processing the untransferred data by the processor, eliminating the need for extra control for dummy data transfer. Therefore, the processing time can be reduced and the load on the processor can be reduced. Further, the system storage can be prevented from being destroyed by the dummy data, which greatly contributes to the improvement of the performance and reliability of the entire system.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention; FIG. 2 is a diagram illustrating the configuration of an embodiment of the present invention; FIG. 3 is a diagram illustrating the configuration of a data shift type buffer having a three-stage configuration; FIG. 5 is a timing chart showing the operation of the buffer control unit in the embodiment of FIG. 2 using a buffer as an example; FIG. In the figure, 10: data shift type buffer 10-1 to 10-M; buffer 12: first interface (transfer destination) 14: second interface (transfer source) 16: processor 18-1, 18-2: register 20: Data bus (2N bit width) 22: Data bus (N bit width) 24: Buffer control unit 26, 28, 30, 48: Selector 32: System storage (SS) 34, 36: Interface control circuit 38: Sampling clock generation circuit 40: Buffer full signal generation circuit 42, 44: FF 46: AND gate 50: Untransferred data detector

Continued on the front page (72) Inventor Tatsuya Yamaguchi 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited

Claims (2)

(57) [Claims] A data holding means (10-1 to 10-) which has a plurality of storage areas with a predetermined capacity and shifts data to a storage area of the next stage when data of a predetermined capacity is arranged in each storage area.
M), a means (12) connected to an output end of the data holding means (10-1 to 10-M) and transferring the data in a plurality of storage area units in one transfer, and a data transfer end Means (24, 18-2) for instructing a storage area in which data remaining without being transferred in the data holding means (10-1 to 10-M) is received when the instruction is received;
And a means (16) for reading data in a storage area corresponding to an untransferred data position based on the instruction. 2. A data holding means (10-1 to 10-) which has a plurality of storage areas of a predetermined capacity and has a predetermined capacity of data in each of the storage areas, and shifts the data to a storage area of the next stage when the data of the predetermined capacity is prepared.
(M) and means (14) connected to the input end of the data holding means (10-1 to 10-M) and transferring data of each division unit obtained by equally dividing the storage area in one transfer. Means (24, 18-1) for instructing a storage area in which data remaining without being transferred in the data holding means (10-1 to 10-M) is received upon receiving a data transfer end instruction. )
And a means (16) for reading data in a storage area corresponding to an untransferred data position based on the instruction.