JPH03271856A - Buffer control system - Google Patents

Abstract

PURPOSE:To simplify the taking-out operation of untransferred data from a buffer and to prevent careless destruction of a system storage (SS) by indicating the 2N-bit area of the buffer last stage and the N-bit area of the buffer first stage as the position in the buffer of data left untransferred in the buffer at the time of receiving a transfer end indication. CONSTITUTION:Registers 18-1 and 18-2 are provided which can be read from a processor 16 which has the function to indicate the 2N-bit area of a last stage 10-M and the N-bit area of a first stage 10-1 as the position in a buffer 10 of data left untransferred in the buffer at the time of receiving the transfer end indication. The position of untransferred data in the buffer is immediately found in accordance with contents of registers 18-1 and 18-2 by the processor 16, and data in buffer areas 10-1 and 10-M corresponding to the untransferred data position indicated by registers 18-1 and 18-2 is directly readably connected to the processor 16. Thus, the operation to take out untransferred data from the buffer by the processor is simplified to prevent the destruction of the SS.

Description

[Detailed Description of the Invention] [Summary] Regarding a buffer control method for processing untransferred data remaining in a data shift type buffer having a data width conversion function, simplifying the operation of a processor to retrieve untransferred data from the buffer. The purpose is to prevent accidental destruction of the SS and SS, and when a transfer end instruction is received, the position in the buffer of the data that remains without being transferred is set to 2N bits of the final stage buffer. A register is provided that has the function of pointing to an area of N bits in the first stage buffer, and the processor learns the buffer location where untransferred data remains from the contents of the register, directly reads the untransferred data, and transfers it to the SS, etc. Configure.

[Industrial Application Field] The present invention relates to a method for processing untransferred data remaining in a data shift type buffer.

With the recent demand for faster computer systems, data buffers are increasingly being used in channel sections to improve data transfer speeds.

Particularly, in a buffer in a channel section, when the bus widths of interfaces located at both ends of the buffer are different, a data shift type buffer that also serves as data width conversion is used. However, with data sheet type buffers that also perform data width conversion, if the number of data to be transferred is not an integral multiple of the number of transfer units of the destination interface, data will remain in the buffer at the end of the transfer. Therefore, an efficient process for extracting the untransferred data remaining in the buffer and sending it to the required location is desired.

[Prior Art] As a conventional data shift type buffer that also serves as data width conversion, the one shown in FIG. 5 is known.

In FIG. 5, reference numeral 10 denotes a data shift type buffer, which in this case has a width of 2N bits and is composed of M=4 stages of buffers. An interface 14 is provided on the left side of the data shift buffer 10, and the interface 14 has a data bus 22 with an N-bit width, and can transfer N-bit data in one transfer. Further, an interface 12 is provided on the right side of the data shift buffer 10, and the interface 12 can transfer data in units of 4N bits in one transfer using a data bus 20 with a width of 2N bits, and can transfer 2N bits of data at the final transfer. .

For example, when data is transferred from the interface 14 to the interface 12 as shown in the figure, the data shift type buffer 10 stores data in the initial stage buffer 10-1 so that the data is aligned to the bus width of 2N bits of the transfer destination interface 12. After confirming that the next stage buffer 10-2 is empty, the data is shifted to the next stage buffer one after another until it is shifted to the final stage buffer 10-4.

Then, 4N bits of data, which is the transfer unit of the transfer destination interface 12, is transferred to the final stage and the buffer 1 at the previous stage.
0-4 and 10-3, the transfer request is raised and the transfer is started. Then, when the necessary amount of data has been transferred, a transfer end instruction is issued to terminate the transfer.

[Problem to be Solved by the Invention] However, in the conventional data shift type buffer control method, in a normal transfer where the number of transferred data is an integral multiple of the number of transfer units of the transfer destination interface, the transfer ends. No untransferred data remains in the buffer when

However, for example, if the transfer unit of the transfer destination interface 12 is 4 bytes and the transfer unit of the transfer source interface 14 is 1 byte, and a transfer of 4N+3 bytes is performed, only 4N bytes, which is an integral multiple of the transfer unit, are normal. The remaining 3 bytes may remain in the data shift type buffer 10.

Therefore, control is required to transfer the untransferred data accumulated in the buffer and terminate the transfer. For this reason, the transfer source interface 14 is controlled to take in the missing 1 byte of dummy data into the buffer, and the 4 byte data, which is the transfer unit of the transfer destination interface, is aligned and sent to the interface 14.

However, the control of the interface 14 at this time is generally performed through the intervention of a processor, which requires many operations, resulting in problems such as an increase in the load on the processor and an increase in transfer time.

In addition, when the transferred data is stored in the system storage (SS), there is also the problem that the data in the system storage may be destroyed by dummy data.

The present invention has been made in view of such conventional problems, and provides a data shift type buffer that simplifies the operation of a processor to retrieve untransferred data from the buffer and prevents the SS from being accidentally destroyed. The purpose is to provide a buffer control method.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention is directed to a buffer control method for a data shift type buffer having the following configuration.

That is, data is transferred in units of 4N bits in one transfer, or in units of 2N bits at the final transfer, to both ends of a data shift type buffer 10 having a storage area of M stages with a width of 2N bits, using a data bus 20 with a width of 2N bits. First thing you can do
Two data transfer interfaces are provided: an interface 12 and a second interface 14 having an N-bit width data bus 22 and capable of transferring data in units of N bits in one transfer.

The data shift type buffer 10 always shifts the data to the next stage area in the same direction when 2N bits of data are collected in the buffer.

In the first interface 12, when data is stored in the data shift type buffer 10, four
If there is an empty N-bit data area, a transfer request signal is sent, and conversely, when data is discharged from the data shift type buffer 10, a transfer request signal is sent if 4N-bit transfer data is available in the final stage and the previous stage. It has the function of sending out.

In the second interface 14, when data is stored in the data type buffer 10, if there is an empty N-bit data area in the first stage, a transfer response signal is sent in response to the transfer request signal; It has a function of sending out a response signal in response to a transfer request signal when N-bit transfer data is available at the final stage during an operation of discharging data from the transfer request signal.

Regarding such a buffer control method, in the present invention,
When receiving the transfer end instruction, data shift type buffer 1
2N bits of the final stage 10-M and N bits of the first stage 10-1 are the positions in the buffer of the data remaining without being transferred in
A register 18-1.18-2 is provided that can be read from the processor 16 with the function of pointing to an area corresponding to bits, and the processor 16 immediately determines the position of untransferred data in the buffer from the contents of the register 18-1.18-2. This is to make it easier to understand.

Furthermore, a configuration is adopted in which the data in the buffer areas 10-1 to 10-M corresponding to the untransferred data positions indicated by the registers 18-1 and 18-2 can be directly readable and connected to the processor 16.

[Operations] According to the buffer control method of the present invention having such a configuration, the following effects can be obtained.

When transferring data from the second interface 14 to the first interface 12 in FIG.
When 2N bits are collected, the buffer control unit 2
Buffer 10-2.10-3.10 by control signal of 4
-4 shifts, the final stage 10-4 and the previous stage 10-
3, when 4N bits worth of data is collected, it is transferred to the first interface 12.

When the buffer control unit 24 receives the completion notification, it checks the empty state of the first stage 10-1 and the last stage 10-M of the data shift type buffer 10, and if untransferred data remains, the corresponding register 18-1. Set bit 18-2. The registers 18 to 1 and 18-2 have bits that indicate the position of untransferred data in the buffer, and by reading this from the processor 16, the position of untransferred data in the buffer can be found. Processor 16 then registers 18-1.
The untransferred data is processed by reading the data in each buffer corresponding to bit 18-2 and writing it into a storage area such as a storage device (SS).

[Embodiment] FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, interfaces 12 and 14 are provided at both ends of data shift buffer 10, and in this embodiment, interface 12 is the destination interface, and interface 14 is the source interface. The bus width of the data bus 20 of the transfer destination interface 12 is 2 bytes (16 bits), and the bus width of the data bus 22 of the transfer source interface 14 is 1 byte (8 bits).
Furthermore, the transfer unit of the transfer destination interface 12 is 4 bytes, and the transfer unit of the transfer source interface 14 is 1 byte.

For data transfer from the interface 14 to the interface 12, the data shift type buffer 10 has a four-stage configuration including a first stage buffer 10-L, a second stage buffer 10-2, a third stage buffer 10-3, and a final stage buffer 10-4. have On the other hand, from interface 12 to interface 14
For data transfer to the first stage buffer 10-5.2
It also has a four-stage configuration including a stage buffer 10-2, a third stage buffer 10-3, and a final stage buffer 10-6.

The first stage buffers 10-1, 10=5 in each transfer direction are connected to the second stage buffer 10-2 via the selector 26. Further, the output of the third stage buffer 103 is applied in parallel to the final stage buffers 10-4 and 10-6 in each transfer direction. Therefore, in the data shift type buffer 10, the first stage buffer 10-1 or 10-5, the second stage buffer 102, the third stage buffer 10-3, and the last stage buffer 10-4 or 10-6 are always arranged in this order. Assume that the data is shifted.

Furthermore, the storage data width of each buffer 10-1 to 10-6 provided in the data shift type buffer 10 is 2 bytes, and the buffer for input/output to the interface 12.14, that is, the first stage buffer 10-1.10. -5 and final stage buffers 10-4 and 10-6, the 1 byte with the lowest transfer order is stored in the upper area H of the 2-byte buffer area, and the remaining 1 byte in the lower area is used to store data in the next transfer order. It is considered an area.

In such a data shift type buffer 10, when data is transferred in the direction from the interface 12 to the interface 14, when taking in data in units of 4 bytes from the interface 12, the first 2 bytes are transferred to the first stage buffer 10-5. Incorporate into. Next, first stage buffer 1
Data 0-5 is shifted to the second stage buffer 10-2 via the multiplexer 25, and the next two bytes are taken into the first stage buffer 10-5.

Thereafter, the buffers are shifted one after another in the same manner while checking the empty state of the next stage buffer (final stage buffer 10-6).
When the data arrives at , the data is sent one byte at a time to the interface 14 in the order of the upper area H and the lower area. Finally, when the transfer of all data is confirmed, the process ends with a transfer completion notification.

Conversely, when transferring data from interface 14 to interface 1/2, data is transferred from interface 14 to interface 1/2.
Byte by byte, data is taken in order from the upper area H1 of the initial stage buffer 10-1 to the lower area, and the data is transferred to the initial stage buffer 10-1.
When 2 bytes of data are ready, they are shifted to the second stage buffer 10-2 via the multiplexer 25. The data shifted to the second stage buffer 10-2 is shifted one after another to the third stage buffer 10-3 and the final stage buffer 10-4, and is then transferred to the final stage buffer 10-4 and the previous third stage buffer 10-3. When 4 bytes of data are ready, it is transferred to the interface 12. Finally, when the transfer of all data is confirmed, the transfer ends with a transfer completion notification. In addition, in the data transfer from the interface 14 to the interface 12, for example, as shown in the upper area H of the first stage buffer 10-1,
In the state in which 1-byte data is stored, shifting to the second stage buffer 10-2 is not performed, but data in the next lower area is waited for and shifting to the second stage and subsequent stages is performed. That is, the data shifted from the first stage buffer 10-1 is not held in intermediate buffers, but is shifted one after another and packed into the final stage, so that the intermediate stage is always kept free for the next data shift. become.

Here, when converting 1-byte width data coming from interface 14 to 2-byte width data and transferring it to interface 12, the number of data to be transferred by interface 12 is 4.
If the number of data actually transferred by the interface 14 is 4N+3 bytes, then the 4N bytes of data are transferred to the interface 12 via the data shift type buffer 10, and the interface 12 transfers 4
Upon completion of the transfer of N bytes, a completion notification is sent and the data transfer is terminated. However, interface 1
2 completes the data transfer, 3 bytes of data remain in the data shift type buffer 10 at this time. Specifically, the upper area H of the first stage buffer 10-1 and the upper and lower areas H, L of the final stage buffer 10-4
Data remains as shown in the shaded area. The reason why untransferred data remains in the data shift type buffer 10 is that the number of data from the interface 14 is 4.
In addition to N+3 bytes, 4N+2 bytes, 4N+1/
(This also occurs in the case of 4N+2 bytes. In the case of 4N+2 bytes, untransferred data remains in the final stage buffer 10-4, and
In the case of +1 byte, untransferred data remains in the upper area H of the first stage buffer 10-1.

In order to detect the position of untransferred data remaining in the data shift buffer 10 at the end of data transfer, the present invention provides registers 18-1 and 18-2. The register 18-1 is provided corresponding to the first stage buffer 10-1, and the register 18-2 is provided corresponding to the last stage buffer 1.
It is provided corresponding to 0-4. This register 18-
1.18-2 is the first stage buffer 10-1 which indicates that untransferred data remains when receiving the transfer end instruction signal.
Pit setting is performed based on the flag F1 of the buffer 10-4 and the flag F2 of the final stage buffer 10-4.

Registers 18-1, 18-2 are connected to processor 16 via multiplexer 30, and
By reading the registers 18-1 and 18-2 from the registers 18-1 and 18-2, the position of the untransferred data remaining in the data shift type buffer 10 can be known. Further, for the processor 16, the upper area H1 of the first stage buffer 10-1 and the lower area of the upper area H1 of the final stage buffer 10-4, in which untransferred data may remain, are read via the multiplexer 30. Accessibly connected. For this reason, processor 16 registers 18-1.
When the position of untransferred data in the buffer is known by reading from the buffer 10-1.18-2, the corresponding buffer 10-1.
By reading the contents of 10-4, all necessary transfer data can be taken in and transferred to, for example, the system storage 32, thereby completing a series of transfer operations.

A buffer control section 24 is shown below the data shift type buffer 10. The buffer control unit 24 generates a sampling clock for data shifting for the interface control circuit 34 for the interface 12, the interface control circuit 36 for the interface 14, and each buffer 10-1 to 10-6 of the data shift type buffer 10. a sampling clock generation circuit 38 for sending data from the interface 14 to the interface 12; An untransferred data detection unit 50 is provided which detects in which position of the initial stage buffer 10-1 and the final stage buffer 10-4 untransferred data remains when a transfer is performed and a transfer end instruction signal is received.

Regarding the buffer control unit 24, the data shift operation in the data shift type buffer 10 by the sampling clock generation circuit 38 will be explained as follows.

FIG. 3 shows a simplified configuration of the data shift type buffer 10 during data transfer from the interface 14 to the interface 12 in FIG. For example, we will take the case where 3 is configured.

A sampling clock is applied to each of the three-stage buffers 10-1 to 10-3 from the sampling clock generation circuit 38 shown in FIG. Specifically, the sampling clock generation circuit 38 starts generating a sampling clock in response to a sampling trigger signal from the interface control circuit 36 of the interface 14 as the transfer source.

FIG. 4 is a timing chart showing data shift operations in the buffers 10-1 to 10-3 in FIG.
It also shows the operation of detecting untransferred data after receiving a data transfer end instruction.

In FIG. 4, Tl, T2. T3. . . is one cycle of the sampling clock, black circles in the buffers 10-1 to 10-3 in the figure indicate a buffer full state, and white circles indicate a buffer empty state.

First, in the first T1 cycle, the second stage buffer 10-
The data already transferred from interface 14 to 2 (4
(3rd data among N bytes) remains, and in this state, the data transferred from the interface 14 in the next T2 cycle is transferred to the buffer 1 by the sampling clock.
Read 0-1. In the next T3 cycle,
A sampling clock is applied to the final stage buffer 10-3. That is, on condition that the buffer full signal of the previous stage buffer 10-2 is on and the buffer full signal of the final stage buffer 10-3 is off, the buffer 10-
A sampling clock is given to buffer 10-2, and the data sent from buffer 10-2 at this time is sent to buffer 1.
Incorporate into 0-3. When the data is taken into the buffer 10-3, the buffer full signal of the preceding buffer 10-2 is turned off, and at the same time, the buffer full signal of the buffer 10-3 is turned on.

In the next T4 cycle, data shift from buffer 101 to buffer 10-2 and buffer 10-
3 to the interface 12.

First, a data shift from buffer 10-1 to buffer 10-2 is generated under the condition that the buffer full signal of buffer 10-1 is on and the buffer full signal of buffer 10-2 is off, and this sampling clock is used to shift data from buffer 10-1 to buffer 10-2. When the data from the buffer 10-1 is shifted into the buffer 102, the buffer full signal of the buffer 10-1 is turned off, and at the same time, the buffer full signal of the buffer 10-2 is turned on.

Assuming that 4N bytes worth of data for the interface 12 are completed by this data shift to the buffer 10-3, an interface transfer timing is generated on the condition that the buffer full signal of the buffer 10-3 is turned on, and the data is shifted to the buffer 10-3. 4N bytes of data are sent to the interface 12. When the pig sending from the buffer 10-3 is completed, the buffer full signal of the buffer 10-3 is turned off.

In the next T5 cycle, data is shifted from buffer 102 to buffer 10-3. That is, on the condition that the buffer full signal of the buffer 10-2 is on and the buffer full signal of the buffer 10-3 is off, the sampling clock is applied to the buffer 10-3, and the data in the buffer 10-2 is transferred to the buffer 10-3. -Shift to 3. When the shift to buffer 10-3 is completed, the buffer full signal of buffer 10-2 is turned off and the buffer full signal of buffer 10-3 is turned on.

In this state, the interface 12 side, which has transferred 4N bytes of data in the T4 cycle, will not send data from the next buffer 10-3 even after waiting for a predetermined number of cycles, so the transfer will end in the Tn cycle, for example. Give instructions. At this time, untransferred data shifted in the T5 cycle remains in the final stage buffer 10-3, and therefore a register indicating the remaining data is set in the next Tn+1 cycle.

Referring again to FIG. 2, the untransferred data detection section 50 provided in the buffer control section 24 detects the initial stage signal obtained from the buffer full signal generation circuit 40 in accordance with the buffer data shift as shown in the time chart of FIG. Buffer 10-1
Based on the buffer full signal of the final stage buffer 10-4, a register set flag indicating the position of untransferred data is generated when a transfer end instruction signal is obtained. That is,
The untransferred data detection unit 50 is provided with an FF 42 for the first stage buffer 10-1 and an FF 44 for the last stage buffer.

The buffer full signal generation circuit 40 supplies the buffer full signal BFI of the first stage buffer 10-1 to the J terminal of the FF42, and the final stage buffer 1 is supplied to the J terminal of the FF44.
A full signal BF4 of 0-4 is given. FF
A clear logic is applied to the terminals 42 and 44 at the time of system start-up, transfer start, etc. Also, FF42
A transfer end instruction signal from the interface 12 side is applied from an AND gate 46 to the CLK terminal of 44 in synchronization with the system clock, and the FFs 42 and 44 are set/cleared by the clock generated by this transfer end instruction signal. At that time, the buffer full signal FB1. The bit state of FB2 is taken in, and the corresponding flag outputs Fl and F2 are sent to the shift register 18-1゜1 via the multiplexer 48.
The bit is set to 8-2.

Incidentally, in the untransferred data detecting section 50 shown in the embodiment of FIG. 2, the first stage buffers 10-1. Final stage buffer 10-
4, if there is untransferred data, the flag is set to 1 and bit 1 is stored in register 18-1. In some cases, untransferred data remains in the upper area H, and in other cases, untransferred data remains only in the upper area H. Therefore, the buffer full signal is expressed in 2 bits, and similarly, the register 18-2 of the final stage buffer 10-4 is also expressed in 2 bits. By using bit representation, the final stage buffer 10 can be used for the processor 16.
It is desirable to be able to notify whether there is untransferred data in both the upper and lower regions of -4, or whether there is untransferred data only in the upper region.

Further, in the above embodiment, the bus width of the transfer destination interface 12 is 2 bytes, and the bus width of the transfer source interface 14 is 1 byte, but the present invention is not limited to this. The same applies to data transfer between appropriate interfaces in which the bus width of the transfer source interface 14 is 2N bits wide and the bus width of the transfer source interface 14 is N bits wide. The same holds true for reverse transfer from interface 12 to interface 14.

[Effects of the Invention] As described above, according to the present invention, in controlling a data shift type buffer having a data width conversion function, even if untransferred pigs remain in the buffer at the end of data transfer, dummy data The transfer can be completed by reading the register indicating the untransferred position in the buffer from the processor without transferring the data, and directly reading and processing the untransferred data in the processor, eliminating the need for extra control for transferring dummy data. Therefore, it is possible to save processing time and reduce the burden on the processor, and it is also possible to prevent the system storage from being destroyed by dummy data, which greatly contributes to improving the performance and reliability of the entire system.

[Brief explanation of drawings]

FIG. 1 is a detailed explanation of the present invention. FIG. 2 is a block diagram of an embodiment of the present invention; FIG. 3 is a block diagram of a three-stage data shift type buffer; FIG. 4 is a block diagram of the three-stage buffer of FIG. For example, a time chart showing the operation of the buffer control section in the embodiment of FIG. 2; FIG. 5 is an explanatory diagram of the prior art. In the figure, 10: data shift type buffers 10-1 to 10-M, buffer 12: first interface (transfer destination) 14: second interface (transfer source) 16: processor 18-1.18-2: register 20: Data path (2N bit width) 22: Data path (N bit width) 24: Variable control unit 26.28, 30.48: Selector 32 system storage (S5) 34.36: Interface control circuit 38: Sampling clock Block generation circuit 40: Buffer full signal generation circuit 42. 44: FF 46: AND gate 50: Untransferred data detection section

Claims (2)

[Claims] (1) A data shift buffer (10) with a 2N bit width and M stages of storage area has a 2N bit wide data bus (20) at both ends of the data bus (20) in units of 4N bits in one transfer or 2N bits in the final transfer. There are two data transfer interfaces: a first interface (12) that can transfer data in units of data, and a second interface (14) that has an N-bit width data bus (22) and can transfer data in units of N bits in one transfer. An interface is provided, and the buffer (10) always shifts the data to the next stage area in the same direction when 2N bits of data are in the buffer, and the first interface (12) shifts the data to the next stage area in the same direction.
When data is stored in the buffer (10), a transfer request signal is sent if there is an empty 4N-bit data area in the first stage and the next stage, and conversely, when data is discharged from the buffer (10), the last stage and the previous stage A transfer request signal is sent when there are 4N bits of transfer data in the buffer, and the second interface (14) sends a transfer request signal to the buffer (
During the operation of storing data in the buffer (10), if there is an empty N-bit data area in the first stage, a transfer response signal is sent in response to the transfer request signal, and conversely, when the data is being discharged from the buffer (10), the final stage In a buffer control method that has a function of sending a response signal in response to a transfer request signal when N bits of transfer data are available in the buffer (10), when a transfer end instruction is received, the data is transferred into the buffer (10). A processor (1
6) Registers that can be read from (18-1, 18-2)
A buffer control method characterized by providing. (2) In the buffer control method according to claim 1, the data in the buffer area (10-1, 10-M) corresponding to the untransferred data position indicated by the register (18-1, 18-2) is read. A buffer control system characterized in that it is connected to a processor (16).