JP2002150763A - Memory device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FIFO free from delay as to a shift register FIFO constituted by connecting plural registers. SOLUTION: In a memory device 10 capable of sequentially transferring data between plural registers and outputting or read out data from the register of the final output stage, data DI inputted to the memory device 10 can be written in the register REG(n-1) of the final output stage. Since the data are stored from the register REG(n-1) of the final stage, a domino FIFO capable of outputting the initial data without waiting for the time required for shifting the data from the register of the input side to the register of the output side can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO memory and its control.

[0002]

2. Description of the Related Art First-in first-out memory (FIFO memory, hereinafter referred to as FIFO memory) is used as a memory for temporarily storing data and sequentially outputting the data to form a queue.
O) are known. A plurality of FIFOs, for example, n registers are sequentially connected so that the output of the (i-1) -th register is supplied to the i-th register. , A memory device capable of sequentially transferring data to an n-th (output stage) register to which data is output. Therefore, for example, in a FIFO to which eight registers are connected, the data input to the FIFO is transmitted by the FI clock for eight clocks.
It is held in the FO and output sequentially.

[0003]

By using the above FIFO, a queue of 8 units of data can be created,
The data held in the FO can be processed in order. However, data initially input to the FIFO is not output from the FIFO until eight clocks have elapsed. That is, there is a delay from the storage of the first data to the output of the data by the number of stages (the number of registers) constituting the FIFO. Therefore, in a system in which data supply is started or in which data to be processed is supplied intermittently, the first few clocks after the system receives data are wasted, and processing of the supplied data is performed without delay. Not suitable for systems you want to get started.

In view of the above, an object of the present invention is to provide a FIFO which can output data without delay after receiving data, and on the other hand, can also hold data corresponding to the number of register stages. And

[0005]

Therefore, according to the present invention, not only data is always transferred sequentially to sequentially connected registers, but also the n-th register, which is an output stage, is given priority. The data is supplied so that a delay caused by sequentially transferring the data from the input stage to the output stage does not occur. That is, of the present invention,
It has n registers, the output of the (i-1) th register is supplied to the i-th register, and data is sequentially transferred from the first register to which data is input to the n-th register to which data is output. In a transferable memory device,
For the n-th register, n can select and supply the output of the (n-1) -th register or the input of the first register
When the data can be written to the n-th register and the (n-1) -th register has no data, the input of the first register is supplied to the n-th register. And a control means for controlling the n-th selecting means.

Therefore, the memory device of the present invention, when it becomes possible to write data to the n-th register,
When there is no data in the (n-1) -th register, the control method includes a step of controlling the n-th register which supplies the input of the first register, that is, the input data of the memory device to the n-th register which is the output stage. Can process the data. For this reason, even if there is no data in the (n-1) -th register, the data to be output next is always stored in the n-th register, which is the output stage. Data can always be output without delay. That is, in a state where all the registers constituting the memory device are not filled with data, as many registers as necessary to hold the input data are sequentially connected, and the time for transferring data between all the registers is reduced. Data can be output without elapse. Therefore, in the memory device of the present invention, the first data can be output without delay, and on the other hand, a queue can be created by holding data of the number of registers.

To sequentially connect as many registers as necessary to hold the input data, select the output of the (i-1) -th register or the input of the first register for the i-th register. I-th selection means that can be supplied as data is provided, and when data can be written to the i-th register by the control means, when there is no data in the (i-1) -th register, the input of the first register is performed. Is supplied to the i-th register. That is, when data can be written to the i-th register, i-
When there is no data in the first register, the memory device can be controlled by a control method including a control step of the i-th register for supplying the input of the first register to the i-th register. In this memory device, data is stored in order from an n-th register, which is an output stage, to an input side, and data is sequentially transferred between registers in which data is stored.

According to the memory device and the control method,
It is necessary to form a circuit so that input data can be supplied to all registers. On the other hand, it is possible to simplify the circuit by limiting the registers to which the input data is supplied, for example, immediately after inputting only to the first input stage and the n-th output stage register. Can be supplied. For this purpose, the n-th selecting means further enables the output of the first register to be selected, and the control means sets the n-th register to the (n-1) -th register when data can be written to the n-th register. When there is no data and there is no data in the first register, the input of the first register is supplied to the nth register. When there is data in the first register, the output of the first register is the nth register. The nth selection means may be controlled so as to be supplied to. That is, in the control step of the n-th register, when data can be written to the n-th register, n-1
When there is no data in the first register and there is no data in the first register, the input of the first register is supplied to the nth register. When there is data in the first register, the output of the first register is output. Supply to the nth register.

In addition to the n-th register, which is the final output stage, when only the first register can accept input data, the number of registers required to hold the input data is equal to the number of registers. Are sequentially connected to a j-th integer (j is an integer satisfying the following condition: n / 2), which is the same or a large integer as n / 2 + 1.
+1 <= j <= n), a j-th selecting means capable of selecting and supplying the output of the (j-1) -th register and the input or output of the (n-j + 1) -th register is provided. When data can be written to the j-th register, there is no data in the (j-1) -th register.
n-j when there is no data in the (n-j + 1) th register
When the input of the (+1) th register is supplied to the i-th register and n−j + 1-th register has data, n
The j-th selecting means can be controlled so that the (j + 1) -th output is supplied to the j-th register. In this memory device, data is sequentially stored in an n-th register which is an output stage and a register closer to a first register which is an input stage, and data is sequentially transferred between registers in which data is stored. You.

[0010]

Embodiments of the present invention will be further described below with reference to the drawings. FIG. 1 shows a schematic configuration of an example of the memory device of the present invention. The memory device 10 includes n (n is an integer) 8-bit registers REG (0) to REG (n
-1) (hereinafter REG or REG (i)
(I is an integer) indicating a register is serially connected, and the input data DI input to the input stage REG (0) is serially transferred to each REG, and the output stage REG (n -1), a function as a FIFO for outputting as output data DOUT is provided. Therefore, the first to nth registers correspond to the 0th to (n-1) th registers in this example, and the same applies to other selectors and the like.

[0011] The memory device 10 further selects the data to be input to each register REG from the 0th to n-1
The n selectors SEL (0) to SEL (n
-1) (hereinafter SEL or SEL (i)
(I is an integer) and indicates a selector).
And a control circuit 11 for controlling the EL. Each S
EL has three inputs, and the i-th SEL (i) is the output of REG (i-1), which is the previous register of input A,
The input data DI of the input B and the output of the REG (i) which is the register at the current stage of the input C can be selected. In addition, “00000000” is input to the input A of the SEL (0) instead of the output of the REG in the preceding stage.

Therefore, the memory device 10 of the present embodiment has
The output of the (i-1) th REG (i-1) is supplied to the REG (i), and when the input A of SEL (i) is selected, data is output from the first register to which the data is input. The memory device is capable of sequentially transferring data to the output n-th register. When data is not input or output, the data held in each REG (i) is maintained by selecting input C. Further, input data DI is input to input B of SEL (i).
Is connected, and when there is no data in the (i-1) th REG (i-1), the input data DI is directly input to REG (i).
Can be stored. That is, the output stage n-
Also in the first REG (n-1), the n-2nd R
If there is no data in EG (n-2), the input data DI
Can be selected and stored in the register REG (n-1) of the output stage. Therefore, the memory device 10 of the present example
In, when there is a write request, the input data DI supplied at that time is first supplied to the output stage REG (n-
Stored in 1). Therefore, when there is a read request, the input data DI input immediately before can be output as the output data DOUT without delay.

FIG. 2 shows eight registers REG0 to REG0.
In the memory device 10 of the present example having G8, data is written and read (read). First, when data from D0 to D2 is supplied to and written to the memory device 10 in order, as shown in FIG. 2A, REG7, which is the output stage, and R, which is the input stage, in order.
Data D0, D1 and D2 are REG-bound to EG0.
7, REG6 and REG5. Next, when new data D3 is written, as shown in FIG. 2B, the contents of REG7, REG6 and REG5 do not change, and data D3 is stored in REG4 next to the next input stage.
Is stored.

On the other hand, if reading is performed in the state of FIG. 2A instead of writing data D3, FIG.
As shown in (c), data D0 of REG7 is DOUT
And the data D1 of REG6 is shifted to REG7, and the data D2 of REG5 is shifted to REG6. Further, when reading and writing are performed simultaneously in the state of FIG. 2A, as shown in FIG.
7 is output to DOUT, the data D1 of REG6 is shifted to REG7, and the data D2 of REG5 is
Are shifted to REG6, and new data D3 is stored in REG5.

As described above, in the memory device 10 of the present embodiment,
At the time of writing in which a write enable signal (hereinafter, a WE signal) is supplied to the control circuit 11 of the memory device 10, input data supplied from the input side DI is REG7, REG.
6, REG5, REG4, REG3, REG2, REG
1 and REG0 are stored in this order. On the other hand, at the time of reading in which a read enable signal (hereinafter, an RE signal) is supplied to the control circuit 11, the output data is always R
Read from EG7. Then, the final stage (output stage, R
Data is stored in order from the REG close to EG7), and when one data is read, the data stored in each REG is controlled to move to the output side one by one.

FIG. 3 shows an example of the control circuit 11 for controlling each of the SEL0 to SEL7 so that data is stored in the register as described above. Control circuit 1 of this example
1 is a signal WA0 to WA7 indicating the position (the number of stages) of a register in which data input from the next input side DI is stored.
, A counter 13 which raises and lowers the pointer P by the WE signal and the RE signal to output appropriate signals WA0 to WA7 from the decoder 12, and a WE signal, an RE signal and WA0 to W
Among the A7 signals, an appropriate selection signal S0 for each of SEL0 to SEL7 by an appropriate combination of signals.
Control logic CTL0 to CT outputting S7C from A
L7 is provided.

FIG. 4 shows the logic in each of CTL0 to CTL7. For example, the output stage R
SEL7 for selecting the data input to EG7 is CT
It is controlled by the selection signals S7A, S7B and S7C from L7. The selection signal S7A is the SEL shown in FIG.
7 is a signal for selecting the data of REG6 at the preceding stage connected to the input A of the REG7, and performs a process of shifting the data from REG6 to REG7. This selection signal S7A is, as shown in FIG. 4, when only the RE signal is supplied, or when the WE signal and the RE signal are output and data is stored in REG6 where the WA6 signal is not output. Is output to That is, the memory device 10 of the present embodiment
When a read request is issued and a write and read request are issued simultaneously and data is stored in the preceding register, the data stored between the registers is stored in a domino manner, as in a normal FIFO memory. The data is shifted and the data stored in the final stage REG7 is output.

The selection signal S7B is, as shown in FIG.
This signal selects the input data DI connected to the input B of the SEL7, and directly stores the input data DI in the REG7. As shown in FIG. 4, the selection signal S7B is supplied with only the WE signal, outputs the WA7 signal, and outputs
This signal is output when no data is stored in G7, or when no data is stored in REG6 in the preceding stage to which the WE signal and the RE signal are supplied and the WA6 signal is supplied. That is, when data can be written to REG7 and no data is stored in REG6, in this example, a WA7 signal is output and no data is stored in REG7 (data is also stored in REG6). When the WE signal is output and REG7 becomes writable, or when the WA6 signal is output and R
When no data is stored in the EG6 and the WE signal and the RE signal are output and the REG7 becomes writable, the input data DI is directly stored in the REG7 of the output stage.

The selection signal S7C is the signal SEL7 shown in FIG.
REG7 connected to the input C of the REG7 itself, and is output when the selection signal S7A or S7B is not output, as shown in FIG.
Is stored. Other SEL0 to S
The same logic is applied to the other CTL0 to CTL6 which supply the selection signal to EL6, respectively. When data can be written to the i-th register among the 0th to 6th REGs, i- When there is no data in the first register, the input data DI, that is, the input of the 0th REG can be stored in the ith REG. Therefore, by applying the logic shown in FIG. 4, as shown in FIG. 2, data is sequentially written from the output stage register to the input stage register, and when data is read, the data is sequentially written from the output stage. A memory device from which data is read can be provided. Note that, in CTL0 that supplies a selection signal to the 0th SEL0, there is no REG at the previous stage, so a FULL signal in which data is stored up to REG0 is output from the decoder 12 and supplied to CTL0.

FIG. 5 shows a different example of the present invention.
The memory device 15 of this example also has n REG (0) to REG (n-1) from the 0th to the (n-1) th, and each R
There are provided n SEL (0) to SEL (n-1) from 0th to n-1th for selecting data to be input to the EG, and a control circuit 11 for controlling these SELs.
In the memory device 15 of this example, the first to n-th registers are integer (n / 2 + 1) th, ie, the REGs from 0 to n-1 are integers (n + 1) / 2 (hereinafter referred to as integers). SEL (0) to SEL (J) of the J-th (J is an integer) have three inputs, and the i-th SEL (i) in this range is a register REG which is a previous stage connected to the input A. The output of (i-1), the initial value DC connected to the input B, "0" in this example, and the register R of this stage connected to the input C
The output of EG (i) can be selected. Note that SEL (0) allows input data DI to be selected instead of the output of the previous stage REG. The REG of the present example is 9 bits, and the input data DI of 8 bits is stored from 0 to 7 bits. The ninth bit is written together with the input data DI, and the flag “1” indicating the presence / absence of data is stored. Is stored.

On the other hand, S + 1 from the (J + 1) th to the (n-1) th
EL (J + 1) to SEL (n-1) are 5 inputs,
The j-th (j is an integer) SEL (j) of this range is REG (j-1) which is the previous register connected to the input A.
And the REG (n-j-1) connected to the input B
(Equivalent to n-j + 1 in the first to n-th systems)
And the output of the REG connected to the input C (n−j−
The input of 1), that is, the output of REG (n−j−2), the initial value DC (“0” in this example) connected to the input D, and the register of this stage connected to the input E An output of a certain REG (j) can be selected. Therefore, in the last stage SEL (n-1), REG
(0), that is, the input data DI
EG (n-1), the first input data DI is also stored in the final stage (output stage) REG (n-1) in the memory device 15 of this example, and at the time of the next read-out. Output data DOU from memory device 15 without delay
T can be output.

FIGS. 6 and 7 show eight registers REG.
Taking the memory device 15 of the present example having REG7 from 0 as an example,
The state where data D0 to D4 are stored is shown. In the memory device 15 of this example, at the time of writing, data is written only to REG7 or REG0,
Data written to 0 is REG6, REG1, REG
5, REG2, REG4, and REG3 are transferred in such a manner as to fill each register. Then, when data is stored in each register, the data is sequentially shifted from REG0 to REG7, and performs the same function as the eight-stage FIFO. On the other hand, at the time of reading, data is always read from REG7.

First, as shown in FIG.
7, REG0 and REG6 store data D0, D2 and D1, and when writing is performed here,
As shown in FIG. 6B, the data D0 and D1 of REG7 and REG6 are left as they are, and REG0 is stored in REG1.
Is transferred to REG0, and new data D3 is stored in REG0.
Is stored. On the other hand, when reading is performed in the state shown in FIG. 6A, as shown in FIG.
The data D1 of REG6 is transferred to REG7 while the data of 0 remains unchanged, and REG6 is in a writable state. Further, when writing and reading are performed in the state shown in FIG. 6A, as shown in FIG.
The data D1 of REG6 is transferred to REG7, and REG6
Is shifted to REG0, and new data D3 is stored in REG0.

Next, as shown in FIG.
Data D0, D are stored in REG0, REG6 and REG1.
3, D1, and D2 are stored. When writing is performed here, as shown in FIG.
The data D0 and D1 of EG6 remain as they are, and REG5
Is transferred to REG1, and REG1 is transferred to REG1.
0 data D3 is transferred, and new data D
4 is stored. On the other hand, in the state shown in FIG.
When reading is performed, as shown in FIG.
The data D0 of REG6 is transferred to REG7, the data D2 of REG1 is transferred to REG6, and the REG1 is in a writable state while the data of G0 remains as it is. Further, when writing and reading are performed in the state shown in FIG. 7A, as shown in FIG.
REG6 data D1 is transferred to REG6.
1 data D2 is transferred, REG1 data D3 is transferred to REG1, and new data D4 is stored in REG0.

FIG. 8 shows an example of the control circuit 11 for controlling each of the SEL0 to SEL7 so that the data is stored in the register as described above. Control circuit 1 of this example
1 is flag data φf of the eighth bit indicating whether data is stored in each register (Qn in the drawing)
[8]), the flag data φf of an appropriate register and
Control logics CTL0 to CTL7 are provided to output appropriate selection signals to the respective SEL0 to SEL7 by combining the WE signal and the RE signal.

FIGS. 9 and 10 show the logic in each of CTL0 to CTL7. For example, S which selects input of data to REG7 which is an output stage
EL7 is a selection signal S7A, S7B, S7 from CTL7.
C, controlled by S7D and S7E. The selection signal S7A is a signal for selecting the data of the previous REG6 connected to the input A of the SEL7 shown in FIG.
A process of shifting data from EG6 to REG7 is performed.
As shown in FIG. 9, the selection signal S7A is output when only the RE signal is supplied and there is data in REG6. That is, when there is a read request to the memory device 15 of the present example and the register at this stage is in a writable state, and there is data in the register at the previous stage, the data stored between the registers as in the FIFO memory. Is shifted in a domino manner, and the data stored in the REG 7 at the last stage is output.

The selection signal S7B is the signal SEL7 shown in FIG.
This signal selects data output from the REG0 connected to the input B. The signal performs a process of transferring data by appropriately bypassing an intermediate register between the input stage and the output stage. This selection signal S7B is, as shown in FIG.
Only the RE signal is supplied, there is no data in REG6, and R
Output when there is data in EG0. That is, when a read request is issued to the memory device 15 of the present example and the register of this stage becomes writable, there is no data in the register of the previous stage, and REG (n−j−1), that is, REG7 of the last stage In, when there is data in REG0, the data in REG0 is stored in REG7 by bypassing REG1 to REG6. For this reason, in the next read request, except for the transfer delay from REG1 to REG6,
The data stored in REG0 can be output as output data DOUT from REG7.

The selection signal S7C corresponds to SEL7 shown in FIG.
Of the REG0 connected to the input C of the memory device 15, that is, a signal for selecting the input data DI of the memory device 15. The input data DI supplied first bypasses the other registers, and the register REG7 of the output stage. Perform processing to transfer to. As shown in FIG. 9, this selection signal S7C indicates that there is no data in REG7,
When there is no data in EG6 and only a write request is issued to the memory device 15, or when writing and reading are simultaneously issued and there is data only in REG7, that is, when there is no data in REG6 or REG0. Is output. That is, there is a write or read and write request to the memory device 15 of the present example, and when the register at this stage is in a writable state, there is no data in the register at the previous stage, and REG (n-j-1), ,
In the last stage REG7, if there is no data in REG0, all registers are bypassed and REG0 is input.
That is, the input data DI of the memory device 15 is
To be stored. Therefore, in the next read request, REG0
The output data DOUT can be output from the REG7 except for the delay of transferring the data from the REG7 to the REG6.

The selection signal S7D corresponds to SEL7 shown in FIG.
Is a signal for selecting the initial data DC connected to the input D of the register D. The flag data φ indicating whether data is stored in the register at the ninth bit of the register.
The processing for clearing f is performed. As shown in FIG. 9, this selection signal S7D has no write request but only a read request, and REG (n-j-1), that is, REG7
Is output when there is no data in REG0.
Therefore, when the data to be written to the REG 7 is not stored in the memory device 15 of the present example, the flag data φf of the data in the REG 7 can be cleared to a state where there is no data.

The selection signal S7E corresponds to SEL7 shown in FIG.
This signal is used to select the output of the REG 7 connected to the input E of the REG 7, and is output when the selection signals S7A to S7D are not output, as shown in FIG. 9, and the data stored in the REG 7 is held. You.

The same logic is applied to the other CTLs 4 to 6 which supply the selection signals to the SEL 4 to SEL 6 respectively.
When data can be written to the j-th register and there is no data in the (j-1) -th register, RE
If there is data in G (n-j-1), the data is input. If there is no data, the input to the register, that is, REG (n-
The data of j-2) can be stored in the j-th REG. For example, for the sixth REG, the selection signal S6A for selecting the data of the previous REG5 is R
Only the E signal is supplied and output when there is data in REG5. Selection signal S6 for selecting REG1 data
B is output when only the RE signal is supplied, there is no data in REG5, and there is data in REG1. REG
The selection signal S6C for selecting the data of 0 is either when there is no data in REG6 and there is no read request. , REG6 have data but REG1 has no data. The selection signal S6D for selecting initial data is output when there is no write request, only a read request, and there is no data in REG1. Further, the selection signal S6E for selecting the own data is the selection signal S6E.
6A is output when S6D is not output, and R
The data stored in EG6 is retained.

On the other hand, for the other CTL0 to CTL3 for supplying a selection signal to SEL0 to SEL3, respectively, when there is no need to bypass an intermediate register,
A process of transferring the data of the preceding register is performed. For example, SEL0 for selecting the input of data to REG0, which is an input stage, is selected from selection signals S0A, S0 from CTL0.
0B and S7C. Select signal S0A
Is a signal at the previous stage connected to the input A of SEL0 shown in FIG. 5, and is a signal for selecting input data DI of the memory device 15 in REG0, and performs processing for storing the input data DI in REG0. This selection signal S0A
As shown in FIG. 10, only the WE signal is supplied (R
E signal is not supplied) and there is no data in REG7 which needs to transfer data prior to this REG0, or when the WE signal is supplied and there is no data in REG0 of this stage, that is, Output when REG0 is writable.

That is, in REG (i) (i is an integer equal to or less than J-1), it is necessary to store data prior to the register while the register REG (i) is in a writable state. ni-1) (from the first to n
In the second system, when there is data in REG (n-i + 1)), the data in the preceding register REG (i-1) is transferred and stored.

The selection signal S0B is SEL0 shown in FIG.
Is a signal for selecting the initial data DC connected to the input B of the register B. The flag data φ indicating whether or not data is stored in the ninth bit of the register is stored in the register.
The processing for clearing f is performed. As shown in FIG. 10, this select signal S0B has no write request, only a read request, and REG (n-1) which shifts data to REG (ni-1) which stores data prior to the register.
-I-2), when there is no data, the register REG
Since the data is transferred from (i) to REG (ni-1) and no longer exists in REG (i), the flag data φf of REG (i) is cleared. In other words, for REG0, only the RE signal is supplied, and if there is no data in REG6, the data in REG0 is written to REG7, so that REG0 has no data and is cleared by signal S0B including flag data φf.

The selection signal S0C is SEL0 shown in FIG.
This signal is used to select the output of REG0 itself connected to the input C of the REG0, and is output when the selection signal S0A or S0B is not output, as shown in FIG.
Data stored in 0 is retained. SEL1 to SE
C3 from other CTL1 which supplies a selection signal to L3, respectively.
The same logic is applied to TL3. When data can be written to the i-th register among the first to third REGs, if there is data in the register that stores data in advance, By shifting the data of the register at the preceding stage, the data is sequentially stored in the registers constituting the memory device 15 according to the algorithm described above. For this reason, in the memory device 15 of the present example, eight registers are sequentially connected, and a FIFO memory is configured by these. However, when the number of data to be stored is smaller than the total number of registers, F in the register corresponding to the number of data
The IFO is configured in a simulated manner, and can output data stored in the memory device 15 without performing unnecessary transfer between registers.

In the memory device 15 of the present embodiment, data is stored in order from the input side and the output side by appropriately bypassing the intermediate register. However, the data is stored by bypassing the intermediate register. The algorithm to be stored is not limited to this example, and REG7, REG
0, REG6, REG5, REG4, REG3, REG
Various algorithms, such as those storing data in order of 2 and REG1, are conceivable. However,
In any case, the first data is output to the output stage REG7.
, It is possible to avoid wasting a clock only for outputting data, thereby preventing wasting time and preventing a domino-type (shift register type) F having no delay.
An IFO (first in first out) circuit can be provided.

[0037]

As described above, the memory device according to the present invention is a memory device having a plurality of registers connected sequentially and having a function as a FIFO. When data can be written, if there is no data in the previous register, the input of the first register, that is, the input data of the memory device is supplied to the register of the output stage and can be written. . Therefore, even if there is no data in the previous stage register, the next output data is always stored in the output stage register. In this memory device, if there is an output request (read request), there is always no delay. Can output data. That is, in a state where all the registers constituting the memory device are not filled with data, as many registers as necessary to hold the input data are sequentially connected, and data is transferred between all the registers. Data can be output without wasting the clock. Therefore, in the memory device of the present invention, the first data can be output without delay while having the function as a FIFO, and the FIFO memory can be incorporated into a system that requires data quickly. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a memory device according to the present invention.

FIG. 2 is a diagram showing how data is stored in the memory device shown in FIG. 1;

FIG. 3 is a block diagram illustrating a control circuit of the memory device illustrated in FIG. 1;

FIG. 4 is a diagram illustrating control logic of a control circuit illustrated in FIG. 3;

FIG. 5 is a block diagram showing an outline of a different memory device.

FIG. 6 is a diagram showing how data is stored in the memory device shown in FIG. 5;

7 is a diagram further illustrating how data is stored in the memory device illustrated in FIG. 5;

8 is a block diagram showing a control circuit of the memory device shown in FIG.

FIG. 9 is a diagram showing control logic of the control circuit shown in FIG.

FIG. 10 is a diagram further illustrating control logic of the control circuit illustrated in FIG. 8;

[Explanation of symbols]

 10, 15 memory device 11 control circuit 12 decoder 13 counter REG register SEL selector CTL control logic WE write signal, RE read signal

Claims (8)

[Claims] 1. An n-th register having n registers, wherein an output of an (i-1) -th register is supplied to an i-th register and data is output from a first register to which data is input. A memory device capable of sequentially transferring data to the n-th register, wherein an n-th selecting means capable of selecting and supplying an output of the (n-1) -th register or an input of the first register to the n-th register; When data can be written to the n-th register and there is no data in the (n-1) -th register, the input of the first register is supplied to the n-th register. Control means for controlling the n-th selecting means. 2. The i-th register according to claim 1, further comprising: i-th selecting means for selecting and supplying an output of the (i-1) -th register or an input of the first register to the i-th register; When the data can be written to the i-th register, if there is no data in the (i-1) -th register, the input of the first register is supplied to the i-th register. A memory device for controlling the i-th selecting means as described above. 3. The n-th selection means according to claim 1, wherein said n-th selection means can further select an output of said first register, and said control means can write data to said n-th register. When there is no data in the (n-1) th register and no data in the first register, the input of the first register is supplied to the nth register, and the data is stored in the first register. A memory device for controlling the n-th selecting means so that when there is, the output of the first register is supplied to the n-th register. 4. The apparatus according to claim 3, further comprising j-th selection means capable of selecting and supplying the output of the (j-1) -th register and the input or output of the (n-j + 1) -th register with respect to the j-th register. The control means, when it becomes possible to write data to the j-th register, there is no data in the (j-1) -th register, and when there is no data in the (n-j + 1) -th register, the n- The input of the (j + 1) -th register is supplied to the i-th register, and when there is data in the (n-j + 1) -th register, the (j-j + 1) -th output is supplied to the j-th register. A memory device for controlling the second selecting means. Here, j is an integer satisfying the following condition. n / 2 + 1 <= j <= n 5. A memory device having n registers, wherein an output of an (i-1) -th register is supplied to an i-th register, and data inputted to a first register is outputted from an n-th register. When data can be written to the n-th register and there is no data in the (n-1) -th register,
A control method for a memory device, comprising a step of controlling an n-th register for supplying an input of the first register to the n-th register. 6. The data processing device according to claim 5, wherein when data can be written to the i-th register, the i-1
A method for controlling a memory device, comprising: a control step of an i-th register for supplying an input of the first register to the i-th register when there is no data in the first register. 7. The control method according to claim 5, wherein in the control step of the n-th register, when data can be written to the n-th register, the n-th register has no data, and the n-th register has no data. When there is no data in the register, the input of the first register is supplied to the n-th register. When there is data in the first register, the output of the first register is supplied to the n-th register. A method for controlling a memory device to be supplied. 8. The method according to claim 7, wherein when data can be written to the j-th register, the j-1
When there is no data in the n-th register and there is no data in the (n-j + 1) -th register, the input of the (n-j + 1) -th register is supplied to the j-th register.
When there is data in the (j + 1) th register, n-
A control method for a memory device, comprising: the j-th control step of supplying a (j + 1) -th output to the j-th register. Here, j is an integer satisfying the following condition. n / 2 + 1 <= j <= n