JPH0511330B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image data transfer circuit that selectively transfers image data to a plurality of image memories via a plurality of buses.

(Prior Art) Conventionally, when selectively transferring image data to image memories connected to multiple buses, the buses are often controlled by bus select data from a CPU (central processing unit). . FIG. 5 shows an image data transfer circuit used in such a case. Bus select data BS from the CPU 1 is given to a decoder circuit 2 which serves as a bus selection circuit. The decoder circuit 2 decodes the bus select data BS and outputs bus enable signals A, B, C, and D for making any one bus usable. The image data is selectively transferred to the image memories 4, 5, . . . via the selector 3 and the selected bus according to the bus enable signals A to D.

By the way, in such a system, when data of one horizontal scanning line is conventionally transferred as image data in one batch, the number n of data that can be transferred in one data transfer is given by the number m of horizontal images in the image memory. , it was necessary to set it within a range where the relationship m≧n holds true. This means that when the number n of transferred image data exceeds the number m of horizontal pixels in the image memory, the transferred data exceeding the number m of horizontal pixels in the image memory must be stored in the next horizontal line of the image memory. This is because the address when reading the image becomes complicated. Therefore, conventionally, there has been a problem that the above-mentioned restriction on the number of image data transfers limits the scope of application of image processing.

(Problems to be Solved by the Invention) As described above, in the conventional image data transfer circuit, the number of data transferred at one time is limited in relation to the number of horizontal pixels of the image memory, and the application of image processing The problem was that the scope was limited.

The present invention is intended to solve such problems, and an object of the present invention is to provide an image data transfer circuit whose data transfer length is not affected by the size of an image memory.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an image memory with m horizontal pixels each connected to a plurality of buses, and an image memory with n pixels (n>
When transferring image data m), a CPU outputs a bus control signal and bus select data of L level for pixels 1 to m and H level for pixels m+1 to n, and a CPU that outputs bus control signals and bus select data of L level for pixels 1 to m, and H level for pixels m+1 to n, and a bus selection circuit that selectively enables one of the buses, and selectively transfers the image data to an image memory connected to the bus via the bus selected by the bus selection circuit. The transfer circuit is provided with a decoder selection circuit that switches these decoders between transfer of pixels from 1 to m and transfer of pixels from m+1 to n based on the bus control signal during transfer of image data of n pixels. It is characterized by

(Operation) A plurality of decoders each decoding a plurality of bus select data are sequentially enabled during one data transfer based on a bus control signal, and each decoder sequentially selects a different bus. Therefore, during one data transfer, image data is sequentially stored in a plurality of image memories connected to these buses. Therefore, even if the number of transferred data exceeds the number of horizontal pixels of the image memory, the excess data can be stored in a different image memory, so the length of the transferred data is not restricted to a specific length. .

(Example) An example of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing the configuration of an image data transfer circuit according to this embodiment.

The CPU 11 outputs two bus select data BS1 and BS2 and a bus control signal BC to the bus selection circuit 12. Bus selection circuit 12
outputs two different bus enable signals A, B, C, and D to the selector 13 in one image transfer cycle based on the bus select data BS1, BS2 and the bus control signal BC. The selector 13 receives input bus enable signals A~
A bus Ba for transferring image data based on D,
Select Bb, Bc, Bd. Image data is transferred to image memories 14, 1 via selected buses Ba to Bd.
5, ... are selectively stored.

FIG. 2 is a diagram showing the bus selection circuit 12 in more detail. The first bus select data BS1 from the CPU 11 is input to the first decoder 21, and the second bus select data BS2 is also input to the first decoder 21.
The signal is input to the second decoder 22. In addition, the bus control signal BC is transmitted to the decoder selection circuit 2.
3 is entered. The decoder selection circuit BC is
Based on the bus control signal BC, decoder enable signals DE1 and DE2 for sequentially selecting the decoders 21 and 22 are output. The two decoders 21, 22 output decoder output signals D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, D11, BS2, inputted bus select data BS1, BS2, inputted, for example, 2-bit bus select data, are inputted.
D12, D13, D14, D21, D22, D2
3, output D24. Decoder output signal D1
1, D21 is a signal for selecting bus Ba,
The signal is input to the NAND circuit 24 and output as a bus enable signal A. Decoder output signal D
12, D22 is a signal for selecting bus Bb,
The signal is input to the NAND circuit 25 and output as a bus enable signal B. Decoder output signal D
13, D23 is a signal for selecting bus Bc,
The signal is input to the NAND circuit 26 and output as a bus enable signal C. Furthermore, the decoder output signals D14 and D24 are signals for selecting the bus Bd, and are input to the NAND circuit 27 and output as the bus enable signal D.

In the image data transfer circuit configured as described above, suppose that the number of pixels in the horizontal direction of the image memories 14 and 15 is m, and if the number of pixels in one horizontal direction of image data n satisfies the relationship m<n. , the following control is performed. For example, the CPU 11 inputs "3" as the bus select data BS1 and "2" as the bus select data BS2 to the decoder 2.
1 and 22 respectively. Additionally, as shown in FIG. 3, the bus control signal from the CPU 11 to the decoder selection circuit 23 is initially at "L" level.
BC is given. As a result, the decoder selection circuit 23 outputs the decoder enable signal DE1 to the decoder 21, thereby enabling the decoder 21. The decoder 21 decodes “3” of the bus select data BS1 and outputs the decoder D.
14 from the "H" level to the "L" level. As a result, the bus enable signal D is output from the NAND circuit 27, and the bus Bd is enabled. Therefore, the image data is selector 1
3. Input to image memory 14 via bus Bd.

On the other hand, the CPU 11 counts the number of transferred data from the start of image data transfer, and when the number of transferred data reaches m, changes the bus control signal BC from "L" level to "H" level as shown in FIG. . As a result, the decoder enable signal DE2 is output from the decoder selection circuit 23, and the decoder 2
Decoder 22 is selected instead of decoder 1. The decoder 22 decodes "2" of the bus select data BS2 and outputs a decoded output D23. This decoder output D23 is outputted as a bus enable signal C via a NAND circuit 26. As a result, the image memory 15 is selected and m
The data from +1st to nth will be stored in the image memory 15.

Incidentally, the truth table of this bus selection circuit is shown in FIG.

In this way, according to this embodiment, even if the number n of image data to be transferred exceeds the number m of horizontal pixels of the image memory, the data portion corresponding to n-m is transferred to another image memory. can be stored in
Therefore, the number of image data to be transferred is not limited by the number of horizontal pixels of the image memory, as is the case in the past.

[Effects of the Invention] As described above, according to the present invention, the number of image data to be transferred is not restricted in relation to the image memory, and therefore it is applicable to a wide range of image processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image data transfer circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a bus selection circuit in the image data transfer circuit, and FIG. 3 is a block diagram showing the configuration of the image data transfer circuit. FIG. 4 is a timing chart for explaining the operation of the transfer circuit, FIG. 4 is a diagram showing the relationship between truth values, and FIG. 5 is a diagram showing the configuration of a conventional image data transfer circuit. 1, 11...CPU, 2...Decoder circuit, 3,
13... Selector, 4, 5, 14, 15... Image memory, 12... Bus selection circuit, 21, 22...
Decoder, 23...Decoder selection circuit, 24-2
7...NAND circuit.

Claims (1)

[Claims] 1. When transferring image data of n (n>m) pixels to an image memory with m horizontal pixels each connected to a plurality of buses, pixels 1 to m are at L level; From m+1 to n outputs H level bus control signal and bus select data.
comprising a CPU, and a bus selection circuit that selectively enables one of the plurality of buses based on the selection data, and is connected to the bus via the bus selected by the bus selection circuit. An image data transfer circuit that selectively transfers image data to an image memory, wherein the decoder is configured to transfer image data of n pixels based on the bus control signal while transferring image data of n pixels.
1. An image data transfer circuit comprising a decoder selection circuit that switches between transfer from 1 to m and transfer from m+1 to n.