JPS6116377A - Memory scanner - Google Patents

Abstract

PURPOSE:To scan a prescribed address area of a memory at a high speed by using plural counters, which has the function to preset an initial value corresponding to a scan area, to generate scanning addresses. CONSTITUTION:Counters CNTX and CNTY generate the abscissa and the ordinate of a two-dimensional memory area respectively and have the preset function. Latches LT1 and LT2 hold lower and upper values of the scanning end address respectively, the latches LT3 and LT4 hold lower and upper values of the scanning start address respectively. A digital comparator DCP1 outputs a signal EQX when address information of the generated abscissa reaches the scanning end position, and a digital comparator DCP2 outputs a signal EQY when address information of the generated ordinate reaches the scanning end position.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory scanning device that scans a predetermined area of memory specified by parameters of two or more dimensions.
In particular, the present invention relates to a memory scanning device capable of high-speed processing.

■Conventional technology For example, when processing two-dimensional image data or character pattern data, the position of each pixel is calculated and it is determined whether the position falls within the processing range while reading and determining the data. and repeat these actions repeatedly. This type of processing is relatively complex, so
It is often processed by a general-purpose microprocessor.

However, it takes a very long time to perform this type of repetitive processing using a microprocessor. Therefore, in order to increase the processing speed, a device configuration is often adopted in which operations such as address calculation are processed by a dedicated hardware device, but this type of device has a complicated configuration and is expensive.

(2) Purpose of the Invention The purpose of the invention is to simplify the configuration of a device that performs high-speed memory scanning for a predetermined address area expressed in two or more dimensions.

■Structure of the Invention In order to achieve the above object, in the present invention, scanning addresses are generated using a plurality of counters that count the addresses of each scanning axis, that is, the main address and subaddress of the memory in the case of two dimensions. do.

The stiff counters are designed to have a function of presetting initial values according to the scanning area so that their output becomes direct address information. Furthermore, in order to determine the end position of scanning for each scanning axis, a plurality of data holding means such as latches are provided, and the values held by these means are compared with the value output by the counter. When the address in the main scanning direction reaches the end position, the counter that counts it is reset to its initial value, and a counting pulse is output to the other counter.

In character pattern recognition, for example, in order to identify the size of the pattern, it is necessary to know the start position, end position, etc. of black pixels (or white pixels) within a predetermined area. Therefore, in one preferred embodiment of the present invention, when the data read from the memory reaches a predetermined value, scanning is terminated at that point. In this way, by reading the value of the counter after the end of the run, it is possible to know the starting position of the black pixel or white pixel.

Further, in a further preferred embodiment of the present invention, a scanning axis switching means for switching the main scanning direction and the sub-scanning direction by 69 times is provided,
Furthermore, the counter is a reversible counter, and can be scanned in any direction along any scanning axis. In this way, by performing scanning in various scanning modes, it is possible to know the start and end positions of black pixels and white pixels, for example, on the lower left and right sides of a character pattern.

With the above configuration, at the end of scanning, the address of the pixel next to the last scanned pixel is held in the i-counter.

Thus, for example, to find the location of the first black pixel found, the contents of the counter must be read and one must be subtracted from it after the scan is completed. Therefore, in a preferred embodiment of the present invention, when the scanning end condition is satisfied, the counting direction of the counter is switched, and the operation is ended with a delay of one clock. That is, when up-counting is performed, after the scanning end condition is satisfied, the counter value is decremented and then the operation is ended. According to this method, address correction is automatically performed (5), so that the contents of the counter match the desired position information, eliminating the need for calculation.

Examples of the invention Hereinafter, the present invention will be described in detail with reference to the drawings.

1st. Figures 1a and 1b illustrate a memory scanning device embodying the invention. Briefly speaking, this device sequentially generates memory addresses in a predetermined two-dimensional area in synchronization with a read clock pulse RD applied from the outside, and when predetermined conditions are met. Repeat until satisfied. In other words, by connecting the address line of the memory to the address output terminals ADR5H and ADR5L of this device, and applying the clock pulse RD to the data read control terminal of the memory, the memory can read data in a preset two-dimensional area. Output sequentially.

When using this device, the memory is arranged in a two-dimensional locus 41 (address) having a size expressed by 2 to the n1 power in the horizontal direction and 2 to the 02 power in the vertical direction (nl and n2 are arbitrary). For example, if nl and n2 are 0 and 9, respectively, two-dimensional coordinates consisting of 1024 (horizontal) x 512 (vertical) can be constructed.

In that case, the memory address is represented by address information consisting of 19-bit binary data, but the upper 9 bits and lower IO bits of the address information are the vertical and horizontal coordinates of the two-dimensional area of the memory, respectively. Corresponds to the coordinates of the direction. Therefore, in the circuit shown in FIG. 1a, address information ADR5H and ADR5L are composed of n2 bits and n1 bits, respectively.

Counters CNTX and CNTY shown in FIG. 1a generate the horizontal and vertical coordinates, respectively, of a two-dimensional memory area. These counters CNTX and CNTY are
This is an up/down counter with a preset function. DATA is the input terminal for preset data, LD is the data preset instruction input terminal, U/D is the up-count and down-count selection instruction input terminal, CK is MJ
An input terminal for several pulses, EN is a counting permission control input terminal, and OUT is an output terminal for counting data, and these terminals operate in positive logic.

The latches LTI and LT2 are provided to hold the lower (horizontal coordinate) and upper (vertical coordinate) values of the scan end address, respectively, and the latches LT3 and LT
4 are provided to hold the lower and upper values of the scan start address, respectively. Digital comparator DCPI
compares the value output by the counter CNTX and the value output by the launch LTI, and the digital comparator DCP2 compares the value output by the counter CNTY and the value output by the launch LT2.

Digital comparison 1DcP1 and DCP2, when the value of input terminal A and the value of input terminal B match, the output terminal Δ=
A high level signal (EQX, EQY) is output to B. That is, the digital comparator DCP1 outputs the signal EQX when the generated horizontal coordinate address information reaches the scan end position, and the digital comparator DCP2 outputs the signal EQX when the generated vertical coordinate address information reaches the scan end position. 'Output Y.

When scanning a two-dimensional area, the horizontal direction is usually set as the main scanning direction and the vertical direction is set as the sub-scanning direction.

However, when detecting the outline of a character pattern, for example, processing may be easier if the main scanning direction and the sub-scanning direction are reversed. Therefore, in this embodiment, a scanning axis switching circuit 100 shown in FIG. 1b is provided. This circuit 10
0 switches between the main scanning direction and the sub-scanning direction in accordance with the signal 5DIR.

In addition, the scanning direction setting circuit 300 is configured to set the scanning direction of the main scanning and sub-scanning (whether to scan in the direction of increasing or decreasing the address).
This is provided.

A determination circuit 200 shown in FIG. 1b determines the scanning area and controls the start and end of scanning.

Hereinafter, the specific usage and operation of this device will be explained with reference to the timing chart of FIG. 2. This device is used by being connected to a path line of a system including, for example, a microcomputer.

The signal CT output from the determination circuit 200 is connected to, for example, an input port of a microcomputer so that the system can refer to it. In addition, the output data line of the memory to be scanned is connected to the input terminal D o of the judgment port @200.
Connect to ut. When actually used, first the address parameters, that is, the upper data 5TADH of the scan start address, the lower data 5TADL, and the upper data EDADH of the scan end address.

and lower data EDADL. When setting these data, nine latch pulses LP are required.
4. LP3. LP2 and LPI are output, and each output data is sent to latch circuits LT/I, LT3 . LT2 and LTI
hold it.

As shown in Figure 3, if the horizontal coordinates of the memory area are assigned to the lower addresses and the vertical coordinates are assigned to the upper addresses, by setting the signal 5DIR to a low level L, the horizontal direction becomes the main scanning direction. The vertical direction becomes the sub-scanning direction, but when the signal 5DIR is set to a high level H, the vertical direction becomes the main scanning direction and the horizontal direction becomes the sub-scanning direction. Also,
When the signal 5UDX and the signal 5uoy are set to high level H, the counters CNTX and CNTY respectively scan in the up-counting direction (normally, the abscissa is from left to right and the ordinate is from top to bottom), but these signal levels When is set to a low level L, the scanning direction is reversed.

In this embodiment, the conditions for terminating the scan are programmable. The condition is set in the latch LT5 as 4-bit data 5CON. These conditions are the signal E
When QX is output, when signal EQY is output,
There are four possible settings: when data [1] (for example, corresponding to a black pixel) is detected, and when data roj (for example, corresponding to a white pixel) is detected.

For example, y f L T 5 data ro, 0,1
．． When OJ is set, the output terminal of the OR gate OR5 becomes high level H when both signals EQX and EQY become high level H or when data "1" is detected. In this case, the output terminal of AND gate AN6 is always at low level L, so when data rOJ is detected,
conditions are masked.

Similarly, data rl, 0, 1 . If OJ is set, the output terminal of OR gate OR3 will always be at a high level H, so if signal EQX is output, the condition
The condition is met as soon as the condition is masked and the signal EQY is output. Also, data ro, 1, 1 . If Oj is set, the output terminal of the OR gate OR4 is always at a high level H, so that when the signal EQY is output, the condition is masked and the condition is met immediately when the signal EQX is output.

Send signal 5DIR to low level L (horizontal direction is main scanning,
The vertical direction is sub-scanning), and the signals 5UDX and 5UDY are set to H and H (both CNTX and CNTY are up-counted), and the data 5CON is rQ, 0, 1 . O
The operation when J is set will be explained.

First, signals LOADX and LOADY are applied. As a result, counters CNTX and CNTY are preset to initial values 5TADL and 5TADH from latches LT3 and LT4, respectively. Halt signal HOLD
is at a high level H, and when the read clock RD is applied, it is applied to the clock terminals of the counters CNTX and CNTY.

Since the signal 5DIR is L, the scanning axis switching circuit 100 changes the signal ENX to 1 at 1-I km, and sets the signal ENY to H only when the signal EQX appears. Therefore,
The counter CNTX is always in a counting enabled state, and the counter CNTY is in a counting enabled state only when the signal EQX appears.

In this state, address information 5TADII + 5TAD
Since L is applied to the address terminal of the memory, here 1
When one pulse RD is output, the contents of the memory at the scanning start position are read out. At the same time, this pulse RD causes the counter CNTX in the counting enabled state to
counts up by 1, and the count value is 5TADL +
Becomes 1. Since the counter CNTY is in a counting prohibited state, it does not respond to the pulse RD and the count value does not change. Similarly, each time a pulse RD appears, the contents of the counter CNTX are updated and the contents of the memory are read each time.

The count value of counter CNTX is the final value EDA of the horizontal coordinate
When DL is reached, comparator DC:P1 outputs a match signal EQX. While signal EQX is at high level ■4, signal LDX
and ENYt becomes high level. When the signal LDX becomes high level H, the initial value 5TADL is again preset to the counter CNTX from the latch LT3, and the count value becomes 5.
Return to TADL. When the signal ENY becomes high level H, the counter CNTY enters the counting permission state, and then the pulse RD
When is applied, the count value of counter CNTY is incremented by 1. That is, the scanning position moves from the right end to the left end of the scanning area in the horizontal direction, and moves one seat down in the vertical direction. Thereafter, the position is updated and the operation continues in the same manner every time the pulse RD is applied.

When the data output from the memory becomes a "1" level during scanning, the output terminal of the AND gate AN5 becomes a high level H, and the output terminal of the OR gate OR5 becomes a high level H. Then, the output levels of the exclusive OR circuits E'XL and EX2 forming the scanning direction setting circuit 300 are inverted, and the signals UDX and UDY, which had been set to the up-count level, both change to the down-count level. . This causes counters CNTX and CN
TY switches to down count mode.

When pulse RD is applied after this, counter CNTX
The count value of is reduced by 1, and the D type flip-flop DF
The high level H applied to the F terminal is set to the output terminal. As a result, the scan end signal CT becomes a high level H, and the hold signal H*LD becomes a low level L. By the hold signal HOLD, the counters CNTX and CNT
Counting of Y stops.

The counter CNTX is set by the output signal of the OR gate OR5.
The purpose of switching the counting direction of CNTY and CNTY is to automatically correct the counted value. That is, for example, when data "1" is found at address ADR8, the count values of counters CNTX and CNTY are changed to ADR3+ by pulse RD for reading memory data at that time.
Becomes 1. Therefore, after setting the counting directions of the counters CNTX and CNTY in the opposite direction, when the operation is ended after one pulse RD appears, the count values of the counters CNTX and CNTY are corrected and the process returns to ADR8.

The address information thus obtained by the counters CNTX and CNTY can be read from the outside (for example, a microcomputer) via the buffer BF.

If data “1” does not exist within the scanning range, the signal EQ
The operation ends when X and EQY appear simultaneously, that is, when the end position HDADH+EDADL of the scanning range is reached.

In other words, by simply setting parameters such as the scan start address and scan end address, a large amount of memory within that range is scanned, and data rlJ or data r
Output the address where OJ existed. This search process is
Since it is done in hardware, it is very fast.

In the above embodiment, the scanning axis switching circuit 100 is used to switch between the main scanning direction and the sub-scanning direction, but a circuit shown in FIG. 4 may also be used. That is, in this example, the address information line connected to the memory and the counter output
In is connected through multiplexers MPX1 and MPX2, and the upper group and lower group of addresses can be exchanged. However, when using this configuration, it is necessary to make the number of bits in the upper group and the number of bits in the lower group of the address the same. Oh,
In this example, Lunch LA 4, Or Gate OR 2
etc. are not necessary.

(2) Effects As described above, according to the present invention, memory can be scanned at high speed using a device with a simple configuration, and is effective for, for example, preprocessing for character pattern recognition.

[Brief explanation of the drawing]

Figures 1a and 1b are block diagrams illustrating a memory scanning device embodying the present invention. FIG. 2 is a timing chart showing an example of operation when using the apparatus shown in FIGS. 1a and 1b. FIG. 3 is a plan view showing the relationship between memory addresses and two-dimensional coordinates. FIG. 4 is a block diagram showing part of a circuit in a modified example of the present invention. 100: Scanning axis switching circuit 200: Judgment circuit (electronic control means) 30o: Scanning direction setting circuit

Claims (6)

[Claims] (1) A first counter with an initial value setting function; a second counter with an initial value setting function; a first data holding means that holds scan end position data of the main address; a scan end position data of the sub address; a second data holding means for holding; a third data holding means for holding at least one of an initial value set to the first counter and an initial value set to the second counter; a count value of the first counter; a first comparing means for comparing the count value of the second counter and the value of the second data holding means and outputting the result; a second comparison means for output; and a counting pulse is sequentially applied to one of the first counter and the second counter, and when the count value of the counter reaches a predetermined value, the value of the third data holding means is transferred to the counter; electronic control means for resetting the counter, giving a counting pulse to the other counter, and repeating these operations until a predetermined condition is met; (2) The predetermined condition is set according to data preset in a register provided in the electronic control means, and the output of the first comparison means is in a predetermined state;
The memory scan according to claim (1), which includes at least one of the following: the output of the comparing means has reached a predetermined state, and the data read from the memory has reached a predetermined value. Device. (3) The memory scanning device according to claim 1, wherein the electronic control means includes scanning axis switching means for switching the scanning order of the main address and the sub address of the memory. (4) The scanning axis switching means selectively connects one of the output line of the first counter and the output line of the second counter to the upper group of memory address lines, and connects the output line of the first counter and the output line of the second counter. Claim 3 comprises a multiplexer for selectively connecting the other of the output lines of the counter to a subgroup of memory address lines.
) The memory scanning device described in paragraph 1. (5) Claims (1) and (2), wherein the first counter and the second counter are reversible counters;
The memory scanning device according to item (3) or item (4). (6) The electronic control means includes a signal inversion means for inverting the counting direction of at least one of the first counter and the second counter, and a delay means, and when the predetermined condition is satisfied, the first counter and the counting direction of at least one of the second counters is reversed, and the operation is terminated after outputting one counting pulse to the counter.
) The memory scanning device described in paragraph 1.