JPS61117673A - System for picture data transfer processing - Google Patents

Abstract

PURPOSE:To attain a processing system where the number of degrees of freedom concerning the position and the size of a partial picture is large, by generating a detection signal during scanning of a data processing range and providing a picture data processing circuit which perform a specific processing selectively in accordance with the detection signal. CONSTITUTION:A scanning control circuit 4 is provided with 4 registers which set X and Y addresses of the start point and the end point of the scan range of a memory 1 and controls the update of X and Y address counters 2 and 3 or the like. Processing range detecting circuits 5 and 6 compare contents of counters 2 and 3 with X and Y address information of the start point and the end point of the data processing range to discriminate whether the designated data processing range is scanned or not and output detection signals. Output data of the memory 1 is inputted to a picture data processing circuit 7, and transfer clocks of picture data are inputted to the circuit 7 from a signal path 12. The control signal which designates a data processing mode is inputted to the circuit 7 also by a signal path 71. The picture data processing circuit 7 subjects input picture data to a specific processing selectively on a basis of signal states of signal paths 45, 53, and 63 in accordance with the designated processing mode.

Description

[Detailed Description of the Invention] [Technical Field] The present invention scans a local range of a memory for storing 5 image data in a literary magazine or other image processing device,
Transfer (read or write) image data for that range and at the same time.

The present invention relates to an image data transfer processing method that selectively processes image data depending on the read position or write position of the image data.

[Prior art]

In character and other image processing, it is possible to take out a partial image from memory or write it into memory, and at the same time,
There are cases where it is desired to partially perform mask processing on the partial image. Traditionally, such partial image transfer and partial processing is performed on a general-purpose processor or dedicated hardware.

When using a general-purpose processor, the processing time is considerably 1.1
Please take a moment! This is a cause of slowing down the overall image processing speed. On the other hand, when using dedicated hardware, although the processing speed can be improved, there is a limitation that there is a lack of freedom regarding the position and size of the partial image to be transferred and the position and size of the processing portion.

〔the purpose〕

It is an object of the present invention to simultaneously transfer partial image data to and from an image data storage memory and to process the partial image data at high speed, An object of the present invention is to provide an image data transfer processing method that has a large degree of freedom regarding the position and size of images.

〔composition〕

The image data transfer processing method of the present invention can achieve the above object, and includes a memory for storing one image data,
An address counter for generating two-dimensional address information of the memory and two-dimensional address information specifying an eleventh scanning range of the memory are set, and the scanning range is two-dimensional.
a scan control circuit that performs initial value setting and update control for the address counter so as to perform dimensional scanning; and a scan control circuit configured to set two-dimensional address information that specifies an arbitrary data processing range of the memory; one or more processing range detection circuits that generate a detection signal while scanning the data processing range by comparing the two-dimensional address information generated by the address counter; and an image read out from the scanning range; The data is characterized by comprising an image data processing circuit that selectively performs specific processing on the image data input into the scanning range in accordance with the detection signal output from each of the processing range detection circuits. That is. Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the image data transfer processing method of the present invention. In this figure, ■ is a memory (RAM) for storing image data, and 2 and 3 are an X address counter and a Y address counter that generate two-dimensional address information (X, Y address information) for the memory l. 4 (This is a scanning control circuit, and the X of the starting point (upper left corner of the scanning range) and end point (lower right corner of the scanning range) of the scanning range (rectangular area on the image plane) of the memory 1.

4 registers for setting Y address information, and the start point address information which is the contents of these internal registers at the start of scanning of memory l as the initial value.

Loading the Y address counters 2 and 3, or updating the X and Y address counters by comparing the values of the X and Y address counters 2 and 3 with the end point address information in the internal register during scanning (loading the X and Y address counters 2 and 3) It consists of a circuit for controlling reloading of starting point X address information and incrementing of a Y address counter. This scanning control circuit 4
takes in the outputs XA, YA of the X, Y address counter 2.3 through signal paths 41.42, and also takes in the outputs XA, YA of the
．． 44 performs initial value loading and updating control for the X, Y address counter 2.3, and further outputs a signal indicating that the scanning range is being scanned to the signal path 45. Signal paths for loading address information into internal registers also exist, but are not shown in ra.

5 and 6 are processing range detection circuits that take in the outputs XA and YA of the X, Y address counter 2.3 via signal paths 51.52 and 61.62, and detect the starting point of the data processing range set in the internal register. By comparing with the X and Y address information of the end point, it is determined whether or not the specified data processing range is being scanned, and a detection signal 1 indicating that scanning is in progress is output to signal paths 53 and 63, respectively. . Each processing range detection circuit 5.6 has the same configuration, and the specific circuit configuration is shown in FIG. 2 and will be explained. In this figure, 101 and 102
is a register 103 in which the X address information and Y address information of the starting point of the data processing range (rectangular area hJj,) are set.
and 104 are the X address information and Y of the end point of the data processing range.
This is a register in which address information is set. 105 and 1
06 is a comparator that compares the output XA (X address of the scanning point) of the X address counter 2 with the values of registers 101 and 103, and 107 and 108 are the Y address counter 3.
This is a comparator that uses the output YA (Y address of the scanning point) and the value of the register 102°to/l as a ratio axis. 109
is a determiner that determines whether or not the data processing range specified by the output signals of the comparators 105 to 108 is being scanned, and its output signal is the detection signal C8, and is connected to the signal path. 53 or 63.

, set the register 101-10/l address information to 1.
The signal path for determining τ is omitted in the figure.

Referring again to FIG. 1, 7 is an image data processing circuit;
The output data of the memory 1 is input through the data input/output path 11 of the memory 1, the image data transfer lock is input through the signal path 12, and the output signals of the scan control circuit 4 and the processing range detection circuit 5 and 6 are input. detection signal) is input. Also.

Control signals specifying the data processing mode are also signal path 71.
Input from The image data processing circuit 7 selectively performs specific processing on the input image data based on the signal states of the signal paths 45, 53, and 63 in accordance with the designated processing mode.

Next, a specific example of the image data transfer process in this embodiment will be described with reference to FIG.

Now, the image data in the memory area T shown in FIG. 3(a) is transferred to the outside.1. At this time, consider the case where the al image data outside the area O is masked and processed into an image framed by white pixels as shown in FIG. 3(b). In this case, the memory area S shown in FIG. 3(a) is specified as the scanning range, and the X and Y address information of the starting point SS and ending point Se are loaded into the internal register of the scanning control circuit 4. Also,
The area T is specified as the first data processing range, and the X and Y address information of the start point Ts and end point Te is stored in the internal register of the processing range detection circuit 5 (register 101 shown in FIG. 2).
-104). Also.

Area 0 is designated as the second data processing range, and the X and Y address information of the start point O5 and end point Oe is stored in the internal register of the processing range detection circuit 6 (register 101-1 in FIG.
04), the signal path 45 is "l" (scanning range S) and both of the signal paths 53 and 63 are "1" (processing range O). (during scanning), the input image data is sent out as output data Douj, and only the 1M path 53 is being scanned.
If so, the processing outputs Pa0'' (white pixel data) and does not send out the valid signal Valid during the period when both signal paths 53 and 63 are ``0'' (while scanning the area outside the processing range T). mode is specified.

The scan control circuit 4 loads the X, Y address information of the scanning range start point Ss set in the internal register into the X, Y address counter 2.3, permits increment by the transfer lock of the X address counter 2, and Incrementing of address counter 3 is suppressed. In this case, memory l
The read/write signal RD/WR of is set to the read state.

By incrementing the X address counter 2, the memory 1 is sequentially scanned in the X direction from the starting point Ss.

The stored data at the scanning point (address designated by XA, YA) is read out and sent to the image data processing circuit 7. When XA increases until it matches the X address information of the end point Se, the scan control circuit 4 reloads the X address information of the start point Ss into the X address counter 2, and increments the Y address counter 3 by one. The X address counter 2 is again incremented by the image data transfer lock, and scanning of the second line in the scanning range T is performed. In this way, the scanning range S is sequentially scanned starting from the top. When the scanning progresses to the end point Se of the scanning range S, the scanning control circuit 4 controls the X9Y address counter 2,
The increment of 3 is prohibited and the scan ends.

The processing range detection circuit 5 sends out a detection signal while scanning the data processing range T (that is, the signal path 53 becomes 'V'). Further, the processing range detection circuit 6 detects the data processing range 0 while scanning it (no. 6 is sent out and the signal path 63 is set to "1" degree. Therefore, the 1 image data processing circuit 7 detects the image data from the data processing range T). A valid signal Valid is sent only when the data is read out, and the read 1fii & data from the data processing range ○ is sent out as output data, and the definition data read from outside the data processing cylinder 1fflO within the data processing range. is masked and output as "O" (white pixel) data.Thus, Figure 3(b)
The data of the processed image shown in is transferred to the outside.

Note that it is also possible to specify the same area as the scanning range S and the data processing range T. Further, as a processing mode of the one-image data processing circuit 7, for example, the first data processing range T
You can specify a mode in which all the Wi image data within the data processing range O is output as is or inverted, or a mode in which the image data in the data processing range O is inverted and output. Since such an image data processing circuit 7 can be easily realized using well-known circuit techniques based on one or more of the descriptions, no specific example is provided.

Furthermore, the embodiment described above has a configuration in which image data is transferred from the memory to the outside. However, the image data transferred from the outside is manually input to the image data processing circuit, the output data Douj is supplied to the data input/output path of the memory, and the memory write operation is performed only when the valid signal Valid is output. It is clear that the other parts have the same configuration as the embodiment described above, and the same image data transfer processing from the outside to the memory is possible.

〔effect〕

Since the image data transfer processing method of the present invention is as described above, it is possible to transfer image data for a specified range of memory, perform partial mask processing, etc. at high speed, and also perform four-scan control. By simply changing the address information set in the circuit and the processing range detection circuit, effects such as the ability to arbitrarily change the scanning range and the position and size of the processing portion of image data can be obtained.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention, and FIG.
This figure is a block diagram of the processing range detection circuit in FIG. 1, and FIG. 3 is an explanatory diagram of range setting and ma data before and after processing. [...Memory, 2...X address counter. 3...Y address counter, 4...Scanning control circuit. 5.6... Processing range detection circuit, 7... Image data processing circuit, 1ot-104... Register, 105
~108 Comparator, 109... Determiner. S...scanning range, T...first data processing range,
Figure 1 Figure 2

Claims (1)

[Claims] (1) A memory for storing image data, an address counter for generating two-dimensional address information of the memory, and two-dimensional address information specifying an arbitrary scanning range of the memory are set, and the scanning range is a scan control circuit that performs initial value setting and update control for the address counter so that the address counter is scanned two-dimensionally, and two-dimensional address information that specifies an arbitrary data processing range of the memory is set, and the two-dimensional address 1 generating a detection signal while scanning the data processing range by comparing the information with two-dimensional address information generated by the address counter;
one or more processing range detection circuits; selectively performing specific processing on image data read from the scanning range or image data written in the scanning range according to a detection signal output from each of the processing range detection circuits; An image data transfer processing method characterized by comprising an image data processing circuit that performs.