JPS63140381A - Video rate projection calculating circuit - Google Patents

Abstract

PURPOSE:To attain an efficient and high speed picture processing by calculating projection data to a video rate from a digital video signal and alternately using one of two memories for storing the projected result and the other for externally reading. CONSTITUTION:A coordinate forming circuit 1 calculates the position on the picture of a picture element inputted from a clock synchronizing with an input picture element and an area setting circuit 2 holds the positions of the start point and the end point of an area to be projected. The output of the circuits 1 and 2 is applied to a projection mask forming circuit 3 to decide whether the inputted picture element is a picture element to be projected or not and the sum to be projected for every line is calculated in one line projection calculating circuit 4 to which the digital video signal is supplied. A memory selection forming circuit 5 forms a memory selection signal from a vertical synchronizing output synchronizing with the input of one screen and outputs to an address selection circuit 6 and an output data selection circuit 9. The circuit 6 switches to an external address or the address of the output of the circuit 1 to store projection data in memories 7, 8.

Description

[Detailed Description of the Invention] [Summary] The present invention outputs image projection data from a digital video signal at a video rate, and in order to make it possible to always read out the memory that stores this data, the present invention uses pipeline processing to perform projection data. The results are calculated and stored in one memory, while the other memory can be read from the outside.

[Industrial Field of Application] The present invention relates to image processing, and particularly to a circuit for calculating projection data of an image at high speed.

Image projection, that is, horizontal summation data of pixel values, is used for image analysis, pattern recognition, etc., but nowadays there is a need to obtain results as fast as possible, and video rate It is required to be able to perform projection calculations that are processed in real time by following the progress, and to be able to read out the results at all times.

[Prior Art] Conventionally, as a technique for calculating the projection of an image, a video signal is frozen, captured as a still image, and a projection result of the image is obtained. An example is shown in FIG.

In this example, the digital video signal is stored in one screen memory (
A microprocessor reads the image and calculates the projection result.

[Problems to be Solved by the Invention] Due to the low processing speed of conventional techniques, projections were calculated by once storing the video signal in memory and then reading the data; however, a frame memory was required. However, there was a problem that the results were not output in real time.

The present invention aims to provide a novel video rate projection calculation circuit that solves these conventional problems.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of a video rate projection calculation circuit according to the present invention.

In the figure, reference numeral 1 denotes a coordinate generation circuit that receives a clock at a frequency at which one pixel is sent and calculates the coordinates of the current pixel.

Reference numeral 2 denotes an area setting register for setting an area from the outside.

3 is a projection mask generation circuit that determines whether the current pixel is in the area to be projected or not.

4 is a one-line projection circuit that projects input pixels.

Reference numeral 5 denotes a memory selection generation circuit which selects a memory after one screen is completed using an external memory selection signal.

Reference numeral 6 denotes a memory address selection circuit that provides an external address or an address output from the coordinate generation circuit 1 to each memory according to the output of the memory selection generation circuit 5.

7 and 8 are memories for storing projection data.

9 is 7 or 8 depending on the output of the memory selection generation circuit 5.
This is an output data selection circuit that selects the output of.

[Function] With the above configuration, first, the horizontal projection is calculated at the video rate by pipeline processing, and two memories, 7 and 8, are provided as memories to hold the projection results, and switching between them is performed in one screen of the image. By synchronizing with the vertical synchronization signal that separates the
You can always access the memory without being aware that there are two memories.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 to 4.

FIG. 2 is a circuit configuration block diagram of an embodiment of the present invention.

In the figure, numeral 11 is a counter (CTR), which uses the horizontal synchronization signal as a clear input and the clock as a clock input.
Outputs the horizontal position coordinates of the current pixel.

12 is also a counter (CTR), which uses the vertical synchronization signal as a clear input, the horizontal synchronization signal as a clock input, and outputs the current position coordinates of the pixel in the vertical direction.

21, 22, 23, and 24 are registers (REG), and the register 21 has an external microprocessor (hereinafter, M
The register 22 stores the vertical projection start position from the external MPU (abbreviated as PU), and the register 23 stores the horizontal projection end position from the external MPU. , the vertical projection end position is stored in the register 24 from the external MPU.

Therefore, the registers 21 to 24 constitute an area setting circuit for the area to be projected.

A comparator (COMP) 31 outputs a high level when the output of the counter 11 exceeds the output of the register 21. 32 is also a comparator (COMP), and counter 1
When the output of register 22 exceeds the output of register 22, it outputs a high level.

33 and 34 are also comparators (COMP), but comparator 33
outputs a high level while the output of the counter 11 is less than the output of the register 23;
When the output exceeds , it outputs a low level.

The comparator 34 outputs the output of the counter 12 from the register 24.

35 is an AND circuit, which outputs a high level when all four inputs are at a high level.

The comparators 31 to 34 and the AND circuit 35 constitute a projection mask generation circuit, and the fact that the output of the AND circuit 35 is at a high level indicates that the pixel coordinates are within the set projection designated area.

41 is a register with clear (RIEG), and
The output of the circuit 35 is used as a clear input, the clock is used as a clock input, and the digital video signal is used as a data input.
When the output of the D circuit 35 is at a low level, "0" is output as data, and when the output of the AND circuit 35 is at a high level, a data input is output.

An adder (ADD) 42 outputs the sum of the output of the register 41 and the output of the register 43.

43 is a clear register (REG) which clears data when the horizontal synchronizing signal is at a low level, uses the clock as a clock input, and uses the output of the adder 42 as a data input.

44 is also a register (REG), which uses the horizontal synchronization signal as a clock input, and register 4 at the falling edge of the horizontal synchronization signal.
Import data from 3. Therefore, the sum of pixel values for each line of horizontal scanning is taken in, and the register 4L 43.
44 and the adder 42 constitute a 1-line projection calculation circuit.

A register (REG) 51 stores a memory selection signal from an external MPU.

52 is also a register (REG), which uses the vertical synchronization signal as a clock input, uses the output of the register 51 as a data input, and changes the memory selection signal after one screen of input is completed.

53 is an exclusive OR circuit (FOR), and register 5
The output of 1 and the output of register 52 are input, and when the two inputs are the same, a read OK double signal is output to the external MPU. Registers 51 and 52 and exclusive OR circuit 53 constitute a memory selection generation circuit.

61 and 62 are selectors (SEL), both of which use the output of the counter 12 and the address from the external MPU as data inputs, use the output of the register 52 as a select input, and output opposite inputs according to the output of the register 52. .

For example, when the output of the register 52 is high level, the output of the selector 61 is the external MPU address, the output of the selector 62 is the output of the counter 12, and when the output of the register 52 is low level, the output of the selector 61 is the external MPU address. counter 1
The output of the selector 62 and the output of the selector 62 become the external MPU address.

70 and 80 are memories (MEMI,
? IEM2), the memory 70 uses the output of the selector 61 as an address input, the output of the register 44 as a data input, stores data in the memory when the output of the selector 61 is the output of the counter 12, and the output of the selector 61 is used as an external input. The memory 80 that outputs memory data when the MPU address is the same as the memory 70 except that the address input is the output of the selector 62; the memory 7o outputs when it stores, and the memory 70 stores when it outputs. .

90 is a selector which selects between the output of memory 70 and the memory 80.
The output of the register 52 is used as a data input, the output of the register 52 is used as a selection input, and read data from the memory 70 or 80 is output.

FIG. 3 is a time chart of the digital video signal in this embodiment.

This embodiment requires that the clock signal be synchronized with the input of each pixel of the digital video signal, as shown in the figure.

FIG. 4 is a diagram showing a horizontal synchronization signal in this embodiment.

As shown in the figure, the period of the horizontal synchronizing signal is 63.5 μs, which is the same as a normal TV signal, and has 525 horizontal scanning lines and 30 frames/sec.

[Effects of the Invention] As explained above, according to the present invention, projection calculation can be performed by pipeline processing, so projection can be calculated without a frame memory, and by providing two memories, the latest projection can be calculated. It becomes possible to constantly access the results, which has an extremely large effect in contributing to increased efficiency and speed of image processing.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit configuration block diagram of an embodiment of the invention, Fig. 3 is a time chart of a video signal in an embodiment of the invention, and Fig. 4 is a diagram of the invention. A diagram showing a horizontal synchronization signal in one embodiment. FIG. 5 is a block diagram of a conventional example. In the drawings, 1 is a coordinate generation circuit, 2 is an area setting circuit, 3 is a projection mask generation circuit, 4 is a 1-line projection calculation circuit, 5 is a memory selection generation circuit, 6 is a memory address selection circuit, 7.8 is a memory, 9 is an output data selection circuit, 11 and 12 are counters (CTR), 21 to 24.41.43.44.51.52 are registers (REG), 31 to 34 are comparators (GOMP), 35 is an AND circuit, 42 is an adder (ADD), 53 is an exclusive OR circuit (EOR), 61 and 62 are selectors (SEL), 70 and 80 are memories (MEMI, MEM2), and 90 is a selector (SEL), respectively.

Claims (1)

[Claims] A circuit for obtaining projection data, which is the horizontal sum of pixel values in a specified rectangular area in an image given in the form of a digital video signal, from a clock synchronized with input pixels. , a coordinate generation circuit (1) that calculates the position of the input pixel on the image, an area setting circuit (2) that holds the positions of the start and end points of the area to be projected, and the output of the coordinate generation circuit (1). and a projection mask generation circuit (3) that determines whether the input pixel is a pixel to be projected based on the output of the area setting circuit (2), and inputs the digital video signal and the output of the projection mask generation circuit (3). A 1-line projection calculation circuit (4) that calculates the sum of pixels to be projected for each line, and a memory selection generation circuit (5) that generates a memory selection signal from a vertical synchronization output synchronized with the input of one screen. a memory address selection circuit (6) which switches between an external address and an address output from the coordinate generation circuit (1) based on the output of the memory selection generation circuit (5); two memories (7) and (8)
And, by the output of the memory selection generation circuit (5), the memory (
7) or an output data select circuit (9) that selects the output of the memory (8), and calculates the projection data from the digital video signal to the video rate, one of the two memories is used for storing the projection result, and the other is used for external storage. A video rate projection calculation circuit characterized in that it is configured to be used alternately for reading from.