JP2001157049A - Image processor and copying machine provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor for executing pattern matching processing at a high speed. SOLUTION: A command and a pointer are inputted to respectively FIFOs 23, 25 and 27, and data generated at a former step is not inputted directly. Thus, the FIFOs 23, 25 and 27 become small-stale in constitution. An IM buffer 40a, an FE buffer 40b, a DB buffer 40c and a PM buffer 40d have their sizes adjusted, according to the processing contents of a corresponding resolution converting part 22, feature-extracting part 24 and a pattern-matching part 26 and are constituted on a memory 40. The FIFOs 23, 25 and 27 have the numbers of stages (depth) adjusted according to the processing contents of the part 22, the part 24 and the part 26. The FIFOs 23, 25 and 27 are provided with output terminals TP1, TP2 and TP3, to easily observe the numbers of the presently using stages of the respective FIFOs 23, 25 and 27. An image processing part 20 consists of hardware for attaining fast processing speed, in response to the operation speeds of a scanner 10 and a printer 80.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus in which processing is divided and speeded up by pipeline processing.
For example, the present invention relates to an image processing apparatus applied to, for example, detecting a prohibited copy in a color copying apparatus, and a copying apparatus having the image processing apparatus.

[0002]

2. Description of the Related Art FIG. 2 is a schematic diagram showing a color copying apparatus as an example of a conventional image processing apparatus. 2. Description of the Related Art A color copying apparatus is provided with a function of detecting a prohibited copy and stopping copying when a copy of a prohibited copy such as a bill is attempted.

[0003] A copying apparatus including this image processing apparatus is a scanner 1 for scanning an object to be copied and outputting input image data S1.
have. The image processing unit 2 and the print processing unit (HOST) 3 are connected to the output side of the scanner 1. The print processing unit 3 receives the input image data S1 and outputs the print output data S
It has the function of outputting as 3. The output side of the print processing unit 3 is connected to a printer 4 for inputting and printing the print output data S3. The print processing unit 3 includes a computer for controlling the scanner, controlling the printer, and controlling the entire image processing unit 2 in addition to the print processing.
Called. Hereinafter, it is called HOST3.

The image processing unit 2 is constituted by, for example, a microcomputer or the like, receives input image data S1, performs predetermined processing based on a program, and determines whether or not the input image data S1 matches a registered image registered in advance. The judgment signal S2 is output. Alternatively, the image processing unit 2 may be realized by a program operating on the computer of the HOST3. Also in this case, the determination signal S2 is output from the image processing unit 2, which is a program.

In this image processing apparatus, for example, an image of a material that should not be copied, such as a bill, is registered in advance as a registration pattern. When the input image data S1 includes a portion that matches the registration pattern, a determination signal S2 is activated. Then, the HOST3 stops the printer 4 or changes the print output data S3 so that a normal copy cannot be obtained, thereby preventing the copy from being obtained.

[0006]

However, the conventional image processing apparatus has the following problems.

[0007] For example, when the processing in the image processing unit 2 is performed based on a program, the processing speed is set to the scanner.
Slow for 1 or 4 operating speed. Therefore, the scanner or the printer has to wait until the processing of the image processing unit 2 is completed. In this case, there is a problem that the high speed of the scanner or the printer cannot be utilized. For this reason, there is a problem that the image processing unit 2 needs to achieve a processing speed that can sufficiently cope with the operation speed of the scanner 1 and the printer 4. In addition, it is required that the image processing be performed continuously in parallel with the scanning, instead of processing after the input image data S1 is completed after the scanner 1 has finished scanning the object to be copied.

[0008] Even when the processing in the image processing section 2 is performed by hardware, there is a problem how to transfer a large amount of image processing data internally. In addition, how the hardware responds to changes in the specifications of input image data (for example, changes in bit length, data length, format, etc.), changes in image processing specifications, and changes in data specifications passed internally along with these changes It was also a problem to respond flexibly. In general, responding to the above problems requires cost and operational overhead.
However, at the same time as the above problems, it is necessary to use the minimum necessary hardware which is optimized and economical in terms of economy, and in terms of performance, an image processing apparatus and a copying apparatus having a high throughput and a high overall throughput. And how to solve these conflicting problems was an issue.

[0009]

In order to solve the above problems, an image processing apparatus according to the present invention receives data, performs predetermined processing, and outputs output data as a result of the processing to a subsequent image processing apparatus. An image processing device comprising a plurality of stages of image processing blocks for performing pipeline processing by sending each as input data to a block, wherein the image processing block, an image processing block next to the image processing block, and , A buffer memory, and a FIFO memory, and output data as a processing result of the image processing block is sequentially transmitted to the next-stage image processing block via the buffer memory in units of a predetermined data amount. The pointer indicating the storage position of the output data in the buffer memory is sequentially stored in the FIFO
The data is transferred to the next image processing block via an O memory.

The image processing block, an image processing block next to the image processing block, a buffer memory, and a FIFO memory;
The image processing block sequentially stores output data, which is a processing result of the block, in the buffer memory in units of a predetermined data amount, and outputs the output data in the buffer memory corresponding to the units of the predetermined data amount. Are sequentially stored in the FIFO memory,
The next-stage image processing block sequentially reads a pointer from the FIFO memory, reads output data from the buffer memory based on the pointer, and performs processing based on the data.

In addition, a command designating the processing content of the next-stage image processing block for the output data is sequentially passed to the next-stage image processing block via the FIFO memory, and the next-stage image processing block is It is characterized in that it is configured to execute processing contents based on the command.

Further, the buffer memory and the FIFO
The memory stores the data storage capacity of the buffer memory and the FIFO according to the processing capacity of the corresponding image processing block.
The number of stages of the O memory can be set respectively, and the FIFO memory includes a FIFO control unit capable of observing the number of data units (currently stored words) stored in the FIFO memory. .

The FIFO control unit includes a stage number setting register, a current storage word counter, a comparator to which the output of the stage number setting register and the output of the storage word counter are input, an output of the comparator and a counter. And the FIFO
And a control logic unit connected to a selector for selecting data to be held in each stage. The number of usable stages of the FIFO memory can be set even after the hardware is determined, and the number of stages can be set according to the set number of stages. It is characterized in that control is possible.

Further, the buffer memory is constituted by a random access memory, and the FIFO memory is constituted by a logic circuit.

Further, the buffer memories corresponding to the plurality of image processing blocks are stored in the same random access memory.
An arbitration unit provided in a memory for arbitrating access to the random access memory from the plurality of image processing blocks is provided.

Further, a copying apparatus according to the present invention includes the above-described image processing apparatus.

The copying apparatus according to the present invention comprises: an image input unit for generating and outputting input image data to be subjected to pattern matching with a registered pattern; a printer; And the above-mentioned image processing apparatus for generating and outputting a pattern matching result, wherein the image processing apparatus is configured by hardware.

[0018]

FIG. 1 is a schematic block diagram of an image processing apparatus showing an embodiment of the present invention.

This image processing apparatus has an image input unit (for example, a scanner) 10 that scans an object to be copied and outputs input image data S10 to be subjected to pattern matching processing with a registered pattern. An image processing unit 20 is connected to an output side of the scanner 10. The image processing unit 20 includes a FIFO 21
have. The FIFO 21 sequentially acquires and stores the pixel data from the input image data S10, and outputs the pixel data in the same order as the acquired order. This is the first processing data S21. This processing data S21 is the same as the input image data. The purpose of the FIFO 21 is to enable smooth input to the image processing unit even if a wait occurs in the subsequent processing. The output side of the FIFO 21 is connected to a first-stage image processing block (for example, a resolution conversion unit) 22. The resolution conversion unit 22 receives the first processing data S21 output from the FIFO 21, and converts resolution, luminance, and hue by a predetermined method. The result of the conversion is the second processing data S22a. This data is written to a first buffer (for example, an image buffer, hereinafter, referred to as an “IM buffer”) 40 a in the memory 40 via the arbitration unit 29. The IM buffer 40a stores a predetermined number of lines.

On the output side of the resolution converter 22, a first FIFO
23 are connected. In the FIFO 23, a first pointer (for example, the first address of the processing data) indicating the second processing data (result of the resolution conversion in this example) stored in the IM buffer 40a in units of a predetermined number of lines. And a command for designating the processing content of the next image processing block for this processing data is written as a set (write operation to the FIFO 23). When the resolution conversion unit 22 writes, for example, four units of processing data in the IM buffer, four sets of commands and pointers corresponding to each processing data are written in the FIFO 23. From the FIFO 23, a signal (referred to as the number of currently stored words) S23-6 indicating how many words of data (a set of commands and pointers) is currently stored is output from the external output terminals TP1 to TP.
3 and can be observed externally. FIF
A second-stage image processing block (in this example, a feature extraction unit) 24 is connected to the output side of O23. Feature extraction unit 24
Retrieves the command and pointer from FIFO23 (FIFO
23 read operations). With reference to the IM buffer 40a in the memory 40 by the pointer, the result of the resolution conversion, which is the second processing data, is read to perform a predetermined feature extraction. The feature extraction result is collected into a predetermined amount as third processing data, and written into a second buffer (for example, a feature extraction buffer, hereinafter referred to as an “FE buffer”) 40b in the memory 40 via the arbitration unit 29.

On the output side of the feature extracting unit 24, a second FIFO 25
Is connected. In the FIFO 25, a second pointer (for example, the first address of the processing data) indicating the position of the processing data in the FE buffer in the memory 40 and a command for the next stage of image processing are written as a set. Further, the current storage word number S25-6 is output from the FIFO 25 to the external output terminals TP5 to TP7, and can be externally observed. A third-stage image processing block (for example, a pattern matching unit) 26 is connected to the output side of the FIFO 25. The pattern matching unit 26 reads a command and a pointer from the FIFO 25. In this example, the pointer is an address of the memory 40. With this address, the FE buffer 40 in the memory 40 is used.
The feature extraction result, which is the third processing data stored in b, is referred to. The feature extraction result is compared with comparison data created based on the feature amount of the registered image. A collection of comparison data is called a database. The database is a DB in the memory 40
It is stored in the buffer 40c. The comparison is performed for all combinations of a set of feature extraction results corresponding to one set of commands and pointers read from the FIFO 25 and a set of data stored in the DB buffer. The result of the pattern matching is stored as fourth processing data in a third buffer (referred to as a “PM buffer”) 40d in the memory 40 via the arbitration unit 29.

The output side of the pattern matching unit 26
3 FIFOs 27 are connected. In the FIFO 27, a third pointer (for example, the first address of the processing data) indicating the position of the processing data in the PM buffer 40d in the memory 40 and a command for the next stage of image processing are written as a set.
Further, the current storage word number S27-6 is output from the FIFO 27 to the external output terminals TP9 to TP11, and can be externally observed.

The output side of the FIFO 27 is connected to a fourth image processing block (for example, MCU) 50 via an interface 28. In addition, MCU 50 is interface 28,
It is connected to the memory 40 via the arbitration unit 29. MCU50
Performs detailed matching at the final stage of image processing using programs and data stored in the memory 31 and the memory 60.
In the detailed matching, a command and a pointer are read from the FIFO 27. In this example, the pointer is an address of the memory 40. With this address, the PM buffer 40 in the memory 40 is
Reference the pattern matching result stored in d. As a result of the detailed matching, when it is determined that the input image includes an image that matches the registered image, the MCU 50 outputs a determination signal S20 from the control unit 30.

The memory 40 has an SR having a predetermined storage capacity.
It consists of AM (Static Random Access Memory) etc.
IM buffer 40a, FE buffer 40b, DB buffer 40
c and the PM buffer 40d. IM buffer
The buffer 40a, the FE buffer 40b, and the PM buffer 40d are provided in accordance with the processing content and processing capacity of the resolution conversion unit 22, the feature extraction unit 24, and the pattern matching unit 26, or the throughput of the processing block on the writing side to the buffer and the reading side. In relation to the throughput of the processing block,
Alternatively, they are set to appropriate predetermined capacities according to the processing speed of the entire pipeline processing. Arbitration Department 29
Has a function of arbitrating access to the memory 40 from the resolution conversion unit 22, the feature extraction unit 24, the pattern matching unit 26, and the interface 28 in a predetermined priority order. The control unit 30 controls the entire system and is connected to the HOST 70 to output the determination signal S20. Memory 31
Is composed of, for example, a ROM (Read Only Memory),
It stores the MCU 50 program and the like. memory
60 is, for example, a dynamic random access memory (DRAM).
y), etc., for storing work data and programs in the MCU 50. Further, the output side of the scanner 10 is connected to the HOST 70. The HOST 70 receives the input image data S10, and outputs the print output data S70 to the printer 80 when the determination signal S20 is inactive.

FIG. 3 is a schematic configuration diagram showing an example of the FIFO 23 in FIG.

The FIFO 23 is a three-input one-output multiplexer (hereinafter referred to as "MUX") 23-1a, 23-2a, 23-3.
a, 23-4a. MUX 23-1a, 23-2a, 23-3a, 2
Input data S22d is input to the first input side of 3-4a. The input data S22d includes an address S22c and a command S22b. MUX 23-1a, 23-2a, 23-3a, 23-
Registers 23-1b, 23-2b, 23-3b, 23-
4b are connected respectively. Register 23-1b, 23-2b,
23-3b and 23-4b input and hold the output signals S23-1a, S23-2a, S23-3a and S23-4a of the MUX 23-1a, 23-2a, 23-3a and 23-4a, and output them. It outputs signals S23, S23-2b, S23-3b, and S23-4b. The output of the register 23-1b is connected to the third input of the MUX 23-1a. The output of the register 23-2b is connected to the second input of the MUX 23-1a,
It is connected to the third input side of MUX 23-2a. The output of the register 23-3b is connected to the second input side of the MUX 23-2a and to the third input side of the MUX 23-3a. The output of the register 23-4b is connected to the second input of the MUX 23-3a and to the third input of the MUX 23-4a. On the second input side of the MUX23-4a,
“0” is input. MUX 23-1a, 2
A FIFO control unit 23-5 is connected to control signal input terminals of 3-2a, 23-3a, and 23-4a. The FIFO control unit 23-5 includes a stage number setting register 23-7 connected to the control signal S30b, a currently stored word number counter 23-6, a currently used stage number S23-6, and a set stage number S23-6.
In this embodiment, a FIFO having a depth of 1 to 4 stages is provided according to the number of stages set in the stage number setting register 23-7, including a comparator 23-8 for comparing 23-7 and a control logic circuit 23-9. Works as The current stage number is output to the outside by the currently used stage number S23-6. The control logic circuit 23-9 receives the FIFO write signal S23-5a, the FIFO read signal S23-5b, the comparison result S23-8 of the comparator 23-8, and the current storage word number counter 23-6. Outputs count-up signal S23-6a, count-down signal S23-6b, and reset signal S23-6c.
MUX23-2a, MUX23-3a, MUX23-4a selection signals
Outputs S23-1c, S23-2c, S23-3c, S23-4c.

The depth of the number of FIFO stages depends on the processing contents of the resolution conversion unit 22, the feature extraction unit 24, the pattern matching unit 26, etc., or the throughput of the write-side processing block to the buffer and the read-side processing block. The number of stages is set to an appropriate predetermined number in accordance with the relative relationship with the throughput or the processing speed of the entire pipeline processing. Further, the width of data (for example, S22d) that can be handled by the FIFO is changed as necessary according to the bit width of the data to be handled.

When this FIFO 23 is set as a FIFO having one depth, when the current storage word number counter 23-6 is zero, that is, when the register 23-1b contains no data, the FIFO 23
Is written, the MUX23-1a is selected by the selection signal S23-1c.
Selects the input data S22d, and the data is written to the register 23-1b. At the same time, the current storage word number counter 23-6 becomes 1 by the count-up signal S23-6a. And FIFO
Is read, the data is read in S23, and the current storage word number counter 23-6 is changed from 1 to 0 by the countdown signal S23-6b.

The operation in the case where the FIFO 23 is set as a two-stage FIFO will be described. In this case, register 23-1
b and register 23-2b are used for storing data. First, the write operation will be described. Current memory word counter 23-6
Is zero, that is, when neither register 23-1b nor register 23-1b contains data, the selection signal S23-1c causes
X23-1a selects the input data S22d, and the data is
Written to -1b. The current storage word number counter 23-6 is counted up from 0 to 1. Next, when the current storage word number counter 23-6 is 1, that is, data is already stored in the register 23-1b and data is not stored in the register 23-2b, the MUX 23-2a is turned on by the selection signal S23-2c. Selects the input data S22d, and the data is written to the register 23-2b. The current storage word number counter 23-6 is counted up from 1 to 2. At this time, MUX23-1a is selected signal S23-1c
Selects S23 and holds the data. Next, the read operation will be described. When the current storage word number counter 23-6 is 2, that is, when data is stored in the registers 23-1b and 23-2b, S23 is read as data. At the same time, the MUX 23-1a selects S23-2b by the selection signal S23-1c, and the data in the register 23-2b is transferred to the register 23-1b. The current storage word number counter 23-6 changes from 2 to 1 by the countdown signal S23-6b. When the current storage word number counter 23-6 is 1, that is, when data is stored only in the register 23-1b, S23 is read as data. The current storage word number counter 23-6 is set from 1 to 0 by the countdown signal S23-6b.
become.

When the currently stored word counter 23-6 is zero
When reading FIFO or current storage word counter
FI when 23-6 is the number of stages set in the stage number setting register 23-7
If the FO is read, the FIFO does not show "EMPT
A signal indicating "Y" or FIFO or "FULL" is output to indicate that the read or write operation is invalid.

The case where the FIFO 23 is set as a FIFO having a depth of three or four steps will not be described because it can be understood from the above description of the case of two steps. The FIFO 25 and the FIFO 27 are configured similarly to the FIFO 23 and perform the same operation. FIFO23, FIFO
The number of stages of the FIFO buffer 25 and the FIFO 27 is set independently according to the capacity of the corresponding IM buffer, FE buffer, and PM buffer. Next, the operation of the image processing apparatus of FIG. 1 will be described. The object to be copied is scanned by the scanner 10, and the input image data S10 is output from the scanner 10. The input image data S10 is sequentially captured and stored in the FIFO 21, and outputs pixel data (first processing data) S21 in the same order as the captured image data.

The image data S21 is input to a resolution conversion unit 22, and the resolution conversion unit 22 converts resolution, luminance, hue, and the like by a predetermined method. Then, from the resolution conversion unit 22,
The converted second processing data S22a, a first pointer (for example, the first address of the processing data) indicating the second processing data, and a next-stage image processing block (the feature extracting unit 24) for the processing data ) Is output in units of a predetermined number of lines. The second processing data is sent to the IM buffer 40a in the memory 40 via the arbitration unit 29, and is stored in the IM buffer 40a corresponding to the first pointer. The first pointer and the command are sequentially taken in and stored in the FIFO 23 as a set for every predetermined number of lines. The currently used number of stages of the FIFO 23 is output to TP1 to TP3.

Commands and pointers are output from the FIFO 23 by the feature extracting unit 24 in the same order as the fetched order. The output command and pointer are input to the feature extraction unit 24. When the command indicates execution of feature extraction, the IM buffer 40a in the memory 40 based on the pointer
From the second processing data is read out via the arbitration unit 29,
Predetermined feature extraction is performed by the feature extraction unit 24.

The feature extraction result generated as a result of the execution by the feature extraction unit 24 is output as third processing data in a predetermined amount. In addition, a second pointer (for example, the first address of the processing data) indicating the third processing data from the feature extracting unit 24 and the processing contents of the next-stage image processing block (pattern matching unit 26) for the processing data Is output in units of a predetermined number of lines. The third processing data is stored in the memory 40 via the arbitration unit 29.
Are sent to the FE buffer 40b in the and stored in the FE buffer 40b corresponding to the second pointer. The second pointer and the command are fetched and stored in the FIFO 25 sequentially as a set for every predetermined number of lines. FIF for TP5-TP7
The number of currently used stages of O25 is output.

Commands and pointers are output from the FIFO 25 by the pattern matching unit 26 in the same order as the fetched order. The output command and pointer are input to the pattern matching unit 26. When the command indicates execution of feature extraction, a memory is stored based on the pointer.
The third processing data is read out from the FE buffer 40b in 40 via the arbitration unit 29. On the other hand, the DB in the memory 40
The comparison data is read from the buffer 40c via the arbitration unit 29. In the pattern matching unit 26, the combination of the read set of the third processing data and the set of the comparison data is compared to perform pattern matching.

The result of the execution by the pattern matching unit 26 is output as fourth processing data. in addition,
From the pattern matching unit 26, a third pointer (for example, the first address of the processing data) indicating the fourth processing data and a command designating the processing content of the next-stage image processing block for the processing data include a predetermined number of lines. Output in units. The fourth processing data is sent to the PM buffer 40d in the memory 40 via the arbitration unit 29, and is stored in the PM buffer 40d corresponding to the third pointer. Third
Pointers and commands are sequentially updated for every predetermined number of lines.
Captured and stored in FO27. FIFO27 for TP9-TP11
Is output.

Commands and pointers are output from the FIFO 27 to the fourth image processing block (for example, MCU) 50 via the interface 28 in the same order as the fetched order. The output command and pointer are input to the MCU 50. The MCU 50 stores the data in the memory 40 based on the pointer.
From the PM buffer 40d inside to the arbitration unit 29, interface 2
The fourth processing data (pattern matching result) is read out via 8. Then, detailed matching is performed using the fourth processing data and the programs and data stored in the memories 31 and 60.

As a result of the detailed matching, if it is determined that the input image contains an image that matches the registered image, the MCU
50 outputs a determination signal S20 from the control unit 30. Judgment signal S20
Is input to the HOST 70, and when the determination signal S20 is active, the HOST 70 thereby stops the printer 80 or changes the output image data S70 so that a normal copy cannot be obtained. Not to be. When the determination signal S20 is inactive, the HOS
Output image data S70 is output from T70. The output image data S70 is input to the printer 80 and printed.

As described above, in this embodiment, (1) When processing data is transferred between image processing blocks such as the resolution conversion unit 22, the feature extraction unit 24, and the pattern matching unit 26, in this case, image processing is performed. Although it is a large amount of data in general because it is handled, it does not need to be transferred directly via FIFO, so a large-scale FIFO is not required, and the processing data specifications (bit length, data length, format, etc.) can be changed flexibly. Can respond to.

(2) For the FIFO 23, FIFO 25, and FIFO 27, a command for designating the processing content of the next image processing block (such as the feature extracting unit 24 and the pattern matching unit 26) is provided along with a pointer on a predetermined line. Since it is output in several units, you can specify the type of execution for the next stage of image processing,
Various image processing can be realized, and it is possible to flexibly cope with a change in image processing specifications.

(3) IM buffer 40a, FE buffer 40b, DB
The buffer 40c and the PM buffer 40d include a resolution conversion unit 22,
The size is adjusted according to the processing contents of the feature extraction unit 24 and the pattern matching unit 26, and the memory 40 can select an optimal one. The FIFOs 23, 25, and 27 are adjusted in depth according to the processing contents of the resolution conversion unit 22, the feature extraction unit 24, and the pattern matching unit 26, and can have an optimal configuration. Output terminals TP1, TP2, TP3 are in FIFO23, 25, 27.
The number of stages currently used by each of the FIFOs 23, 25, and 27 can be easily observed, which is useful for debugging, performance evaluation, acquisition of judgment information for optimally setting the number of stages, state check, and the like.

(4) The FIFO control unit includes a stage number setting register 23-7, a current storage word counter 23-6, and a comparator 23- which receives the output of the stage number setting register and the output of the storage word counter as inputs. 8, a selector for selecting the output of the comparator, the counter, and the data to be held in each stage of the FIFO.
23-1a, 23-2a, 23-3a, and 23-4a, and a control logic unit 23-9 connected thereto, so that the number of usable stages of the FIFO memory can be set even after the hardware is determined. In addition, since control can be performed according to the set number of stages, the number of stages can be changed according to the processing status even after hardware is implemented, and an optimal system can be tuned by software.

(5) IM buffer 40a, FE buffer 40b, D
B buffer 40c and PM buffer 40d are configured by RAM,
Since the FIFOs 23, 25, and 27 are constituted by logic circuits, it is possible to easily cope with a change in the capacity of the data buffer accompanying a change in processing data specifications. According to the RAM, the cost per unit bit is low and economical. On the other hand, each FIFO is directly connected to the preceding and succeeding image processing blocks, and pointers and commands are immediately passed from the preceding and succeeding image processing blocks without going through an access process required for a memory. It is fast in that sense.

(6) The IM buffer 40a, the FE buffer 40b, the DB buffer 40c,
And the PM buffer 40d is provided in the same RAM 40, and the arbitration unit 29 for arbitrating access to the RAM 40 from the plurality of image processing blocks is provided. In addition, while contributing to mounting space, wiring, chip cost, etc. and improving economic efficiency, contention for access between the image processing blocks is avoided, and the operation failure of the image processing apparatus does not occur.
In addition, since one image processing block can access the RAM without knowing the state of the other image processing blocks, the independence of the processing of each image processing block is maintained, and pipeline processing with good overall throughput is easily performed. realizable.

(7) The image processing apparatus 20 is provided between the scanner 10 and the HOST 70, and is connected to the printer 80 from the HOST 70. As a result, the image processing apparatus 20 can continuously perform image processing in parallel with scanning without stopping the operation of the scanner or the printer, and a copying apparatus with a high throughput as a whole can be obtained. Further, such image processing that handles a large amount of data can be realized at high speed with small-scale hardware.

(8) In (7), the image processing unit 20
Is constituted by hardware, it is possible to provide an image processing apparatus which operates at higher speed and with higher reliability than the conventional image processing apparatus using software, and uses an image processing apparatus utilizing the features of (1) to (6). This makes it possible to obtain a copying apparatus having a high throughput as a whole by making use of the processing capability of the scanner 10 and the printer 80, which have been increasing in speed in recent years.

The image processing apparatus according to the present invention is not limited to a copying apparatus, but may be applied to, for example, a bill validator for identifying the authenticity and type of bills, and an identifying apparatus for identifying the authenticity and type of securities. it can.

[0048]

As described in detail above, according to the present invention, (1) When processing data is transferred between image processing blocks, generally a large amount of data such as image processing is directly transmitted.
Since the data is not transferred via the FIFO, a large-scale FIFO is not required, and the specification (bit length, data length, format, etc.) of the processing data can be flexibly changed.

(2) A command for specifying the processing contents of the next-stage image processing block is output to the FIFO memory together with the pointer in units of a predetermined number of lines, so that the type of execution for the next-stage image processing is specified. It is possible to implement various image processing and flexibly cope with a change in image processing specifications.

(3) Since the size of each buffer memory is adjusted according to the processing content of the corresponding image processing block, the memory can be optimized. In addition, each FI
The number of stages (depth) of the FO memory is adjusted in accordance with the processing content of the corresponding image processing block, so that an optimal configuration can be obtained. Each FIFO memory is provided with an output terminal, and the number of stages currently used in each FIFO memory can be easily observed.
It is useful for debugging, performance evaluation, obtaining judgment material for optimally setting the number of stages, and checking the status.

(4) Since the FIFO control unit has a predetermined configuration, even after the hardware is determined,
The number of usable stages of the O memory can be set, and control according to the set number of stages is possible. Thus, even after the hardware is implemented, the number of stages can be changed according to the processing status, and the optimal system can be tuned by software.

(5) Since each buffer memory is constituted by a RAM and the FIFO memory is constituted by a logic circuit, it is possible to easily cope with a change in the capacity of a data buffer accompanying a change in processing data specifications. According to the RAM, the cost per unit bit is low and economical. On the other hand, each FIFO is directly connected to the preceding and succeeding image processing blocks, and pointers and commands are immediately passed from the preceding and succeeding image processing blocks without going through an access process required for a memory. It is fast in that sense.

(6) A plurality of buffer memories corresponding to a plurality of image processing blocks are provided in the same RAM, and arbitration means for arbitrating access from the plurality of image processing blocks to the RAM is provided. Therefore, by constructing a plurality of buffers with the same RAM, contributing to mounting space, wiring, chip cost, etc. and improving economic efficiency, contention of access between image processing blocks is avoided, and the image processing apparatus is improved. There is no operation failure. In addition, since one image processing block can access the RAM without knowing the state of the other image processing blocks, the independence of the processing of each image processing block is maintained, and pipeline processing with good overall throughput is easily performed. realizable.

(7) The image processing apparatus of the present invention is provided between the scanner and the HOST. As a result, the image processing apparatus can continuously perform image processing in parallel with scanning without stopping the operation of the scanner or the printer, and it is possible to obtain a copying apparatus having a high throughput as a whole. Further, such image processing that handles a large amount of data can be realized at high speed with small-scale hardware.

In (8) and (7), since the image processing apparatus is constituted by hardware, it is possible to provide an image processing apparatus that operates at higher speed and with higher reliability than the conventional image processing apparatus using software. By using an image processing apparatus utilizing the features of (1) to (6), it is possible to obtain a copying apparatus having a high throughput as a whole by utilizing the processing capability of the scanner 10 and the printer 80, which have been increasing in speed in recent years.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional image processing apparatus.

FIG. 3 is a configuration diagram of a FIFO 23 in FIG. 1;

[Explanation of symbols]

21, 23, 25, 27 FIFO 22 Resolution conversion unit (image processing block) 24 Feature extraction unit (image processing block) 26 Pattern matching unit (image processing block) 28 Interface 29 arbitration unit 30 control unit 40 memory 40a IM buffer (buffer) ) 40b FE buffer (buffer) 40c DB buffer (buffer) 40d PM buffer (buffer) 50 MCU (image processing block) TP1 to TP11 output terminals

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 1/00 G06F 15/64 450D 5C077 15/66 L (72) Inventor Masamichi Uehara Yamato 3 Suwa City, Nagano Prefecture 3-5-5 Seiko Epson Corporation (72) Inventor Ryuichi Tsuji 3-3-5 Yamato Suwa City, Nagano Prefecture F term in Seiko Epson Corporation 2C087 AA09 AB04 BA03 BA07 BC01 BC02 BC05 BC07 BD24 DA13 2H034 FA01 5B047 AA01 AB04 EA01 EA07 EB07 EB14 5B057 AA11 BA24 CH05 CH11 DC22 DC25 DC32 DC36 5C062 AA05 AB22 AB41 AB42 AB43 AC04 AC08 AC22 AE03 BA00 BA04 5C077 LL14 LL18 MP08 NN09 NP05 PP03 PP35 PP02 PP65 PP02

Claims (9)

[Claims] 1. A multi-stage image processing apparatus for performing pipeline processing by inputting data, performing predetermined processing, and transmitting output data as a result of the processing as input data to a subsequent image processing block. An image processing apparatus including a block, comprising: an image processing block; an image processing block next to the image processing block; a buffer memory; and a FIFO memory. The output data, which is the processing result, is sequentially passed to the next-stage image processing block via the buffer memory in units of a predetermined data amount, and a pointer indicating the storage position of the output data in the buffer memory is sequentially stored in the FIFO. An image processing device configured to transfer the image data to the next image processing block via a memory. . 2. A plurality of stages of image processing for performing pipeline processing by inputting data, performing predetermined processing, and transmitting output data as a result of the processing as input data to a subsequent image processing block, respectively. An image processing apparatus including a block, comprising: an image processing block; an image processing block next to the image processing block; a buffer memory; and a FIFO memory. Indicates output data, which is a processing result of the block, is sequentially stored in the buffer memory for each unit of a predetermined data amount, and indicates a storage position of the output data in the buffer memory corresponding to each unit of the predetermined data amount. Pointers are sequentially stored in the FIFO memory, and the next-stage image processing block is stored in the FIFO memory An image processing apparatus configured to sequentially read a pointer from the buffer memory, read output data from the buffer memory based on the pointer, and perform processing based on the data. 3. A command for designating the processing contents of the next-stage image processing block for the output data is sequentially passed to the next-stage image processing block via the FIFO memory, and the next-stage image processing block is 3. The image processing apparatus according to claim 1, wherein the apparatus is configured to execute processing contents based on a command. 4. The buffer memory and the FIFO memory according to a processing capability of a corresponding image processing block.
The data storage capacity of the buffer memory and the number of stages of the FIFO memory can each be set, and the FIFO memory is capable of observing the number of data units (currently stored words) stored in the FIFO memory. The image processing apparatus according to claim 1, further comprising a control unit. 5. The FIFO control unit includes: a stage number setting register; a current storage word counter; a comparator which receives an output of the stage number setting register and an output of the storage word counter; and an output of the comparator and a counter. And a control logic unit connected to a selector for selecting data to be held in each stage of the FIFO. The number of available stages of the FIFO memory can be set and the number of set stages can be set even after hardware is determined. The image processing apparatus according to claim 4, wherein the control can be performed according to the following. 6. An image processing apparatus according to claim 1, wherein said buffer memory is constituted by a random access memory, and said FIFO memory is constituted by a logic circuit. 7. An arbitration unit in which the buffer memories corresponding to the plurality of image processing blocks are provided in the same random access memory, and arbitrates access to the random access memory from the plurality of image processing blocks. An image processing apparatus comprising means. 8. A copying apparatus comprising the image processing apparatus according to claim 1. 9. An image input unit for generating and outputting input image data to be subjected to pattern matching with a registered pattern; a printer; inputting the input image data and performing pattern matching with the registered pattern; A copying apparatus comprising: the image processing apparatus according to claim 1, which generates and outputs a pattern matching result, wherein the image processing apparatus is configured by hardware.