JPS6367604A - Process signal converter - Google Patents

Abstract

PURPOSE:To improve the control processing response by storing the logic signals or the logical data corresponding to a process input signal in an associative memory and having output of the corresponding logic signals or logical data based on the input process signal pattern and by means of a retrieving function of the associative memory. CONSTITUTION:The process signals supplied to a process signal converter 100 are given to an associative memory as the data for retrieval. The associative memory stores an input pattern of the process signal and combinations of logic signals to be produced in response to said input pattern. Then the associative memory can read out the value of the retrieved contents after designating said contents (retrieving key) instead of an address. Thus the associative memory retrieves and delivers the corresponding logic signal at a high speed with the input process signal used as a retrieving key. As a result, the process input signal and its corresponding logic signal (or logical data) are converted at a high speed. Then the load of a control computer 500 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a process signal input device, and particularly to a process signal conversion device suitable for a control system that requires high-speed process signal analysis.

[Conventional technology]

Input analysis of process input signals in conventional process control involves generating logic signals or logic data corresponding to events that occur in the process using an input analysis program that performs bit checks on input signals that are captured periodically or by interrupts. The corresponding processing was executed accordingly. However, no consideration was given to a decrease in processing responsiveness due to an increase in the overhead of program execution due to an increase in the number of input signals and an increase in the number of signal bumps to be inspected. In addition, examples of related devices of this type are as follows.

For example, JP-A-56-17422 is cited.

[The good luck point that the invention attempts to solve]

In the above conventional technology, input signals generated in the process are input as bit bangs to the control computer 500 from the digital input control device (hereinafter referred to as DI controller) 116 as shown in FIG. 2, and the input is inspected by an input analysis program. Therefore, the overhead of program execution when input signals increase cannot be ignored, and as the amount of signals to be processed increases, the processing responsiveness of the control computer deteriorates.

An object of the present invention is to solve the above-mentioned problems in terms of hardware.

[Means for solving problems]

The above purposes are the input signals that occur in the process.

FIG. 3 shows a process signal conversion device 100 that stores the correspondence between logical signals or logical data to be created in response to the combination button in an associative memory, and converts the two as needed using the search function of the associative memory. This is achieved by providing it between the DI controller 116 and the control computer 500 as shown.

[Effect]

The process signal input to the process signal conversion device 100 is input to the associative memory as data for retrieval.

The associative memory stores input buttons of process signals and combinations of logic signals to be generated in response to the input buttons. Associative memory is a type of memory that allows you to specify a search content (search key) instead of an address and read its value, whereas conventional memory specifies an address in memory and reads its contents. . The above-mentioned content addressable memory uses the input process signal as a search key to quickly search and output the corresponding logic signal, so the conversion of the process input signal and the corresponding logic signal (or logic data) is realized and controlled at high speed. The load on the computer 500 is reduced. Furthermore, the correspondence between process signals and logic signals can be established by simply rewriting the contents of the associative memory.

〔Example〕

Hereinafter, process signal conversion device 100 (hereinafter device 100
The device 100 basically consists of an associative memory 111 (hereinafter referred to as C), as shown in FIG.
A mask button memory 112, an event number memory 109, and a control circuit 107 that controls their operations. The control circuit 107 is composed of a logic element such as an IC and a clock circuit. CAMIII is connected in advance to the data bus 11. from the control computer 500.
As shown in FIG. 4, the detection status button (+1
10) is used as index data, and the corresponding logical event &1111 is written as read data. Also, in the mask button memory 112, current status data sent from the DI controller 116 and AND (A
The mask button to take (ND) is stored in memory as shown in FIG.

The operation of the apparatus 100 will be described in detail below with reference to the block diagram of the apparatus 100 shown in FIG. 1 and the flowcharts shown in FIGS. 7 and 8.

The operation of the device 100 consists of a logical event detection operation and a logical event reading operation. First, the logical event detection operation will be explained with reference to the flowchart of FIG. 7, focusing on the operation of the control circuit 107.

The control circuit 107 periodically issues a command to the DI controller 116 via the control line 133 to output the current status to the current status register 115 (step 701).

Next, the write address register 105 is set to the pace register 2.
From (106), the start address of the event number memory 109 is loaded (step 702).

Next, the start address of the mask pattern is loaded into the successive address register 102 from the pace register (lO3) (step 703), and the following process is repeated.

First, by outputting the contents of the read address register 102 to the address bus 101 (step 704) and sending a read a command to the mask button memory 112 (step 705), the mask pattern is transferred from the mask button memory 112 to the mask register 114. Output. Next A N
A signal for ANDing the contents of the current status register 115 and the contents of the mask register 114 is sent to the D circuit 117 (step 7o6). The output button from the AND circuit 117 is sent to the search register 113 and further transferred to CAMIII (step 707).

CAMIII performs an associative search for the detected event number from the output button of the AND circuit 117 and sends it to the result register 108 (step 708).The result register 108 outputs the event number to the data bus 110 according to a command from the control circuit 107. (Step 709), control circuit 10
7 outputs the contents of the write address register 105 to the address bus 101 (step 710), and then sends a write command to the event number memory 109 (step 711) to convert the detected event number to event N.

The data is written in the memory 109 in the form shown in FIG. Then, the values of the detected event number counter 145 and the write address register 105 are set to 1t! l (step 712)
. The above operations are repeated until all mask buttons in the mask button memory 112 are read out (step 713).
The above is the logical event detection operation.

Next, regarding the logical event read operation, the control circuit 107
The operation will be explained with reference to the flowchart of FIG. 8. Detection event number transmission command 14 from control computer 500
2 enters the control circuit 107 (step 801), the control circuit 107 loads the start address of the event number memory 109 from the pace register 2 (106) into the read address register 102 (step 802), and performs the following processing. Repeat. First, read address register 10
2 to the address bus 101 (step 8
03), read command 12 to event number memory 109
7 (step 804), the event NO.
The detected event number is sent from the memory 109 to the data bus 110.
Output. The value of the detected event number counter 145 is then incremented by -1° and the value of the read address register is incremented by 1 (step 805).
This is repeated until the value of 5 becomes φ (step 806).

The above is the logical event number read operation.

By repeating the above operations, the device 100 acquires the current status data (bit bang) taken in from the DI controller 116.
Based on this, the stored logical event number corresponding to the current status data is sent to the control computer at high speed via CAMIII.

The control computer 500 can directly execute interrupt processing using the vector interrupt function based on the received logical event number, or by software, without going through the device 100. Control computer 5
00, the responsiveness is significantly improved compared to the method of analyzing current situation data using software. Also, if the correspondence between the bit bang of the current status data and the logical event number is changed, the CAM
It is easy to make changes as it is only necessary to rewrite the contents of III.

In addition, in this embodiment, the logical event number is determined from the current status data.
The search function of CAMIII was used as a function to search, but instead of CAMIII, logic elements and RAM or RO
The function of CAM III may be realized by configuring a search circuit using M memory.Also, in this embodiment, the device 100 is provided separately from the control computer 500 and the DI controller 501, but either one of them may be used. It may also be realized as an integrated type by incorporating it into the system.

〔Effect of the invention〕

According to the invention, the combination of input signals from the process is
Since it can be input into a computer after being converted into a corresponding logic signal or data at high speed, the overhead of process signal input analysis processing in the control computer can be reduced, which has the effect of improving the responsiveness of control processing. Further, changes or additions to the correspondence between input signals and logic signals by changing the connections of process signal lines or the like can be easily made by simply rewriting the content of the associative memory.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a process signal conversion device according to an embodiment of the present invention, Fig. 2 is an explanatory diagram showing a conventional process signal detection method, and Fig. 3 is an explanation showing a process signal detection method proposed by the present invention. 4 is a table showing the contents of the memory data of CAMIII, FIG. 5 is a table showing the contents of the mask button memory, and FIG. 6 is a table showing the contents of the event number memory 10.
7 is a flowchart showing the logic event NO detection operation by the control circuit 107, and FIG. 8 is a table of the detection event NOs in the control circuit 107)
It is a flowchart which shows No read operation.

Claims (1)

[Claims] 1. In a computer system consisting of a process input/output device and a computer, a logic signal or logic data corresponding to a process input signal pattern is stored in an associative memory, and the content of the associative memory is stored based on the input process signal pattern. 1. A process signal conversion device that outputs a corresponding logic signal or logic data using a search function.