JPH03204744A - Address converting mechanism - Google Patents

Abstract

PURPOSE:To prevent a useless updating processing by updating the table information only when a bit of a table discriminating means is not set, although a bit of a task discriminating means is set. CONSTITUTION:At the time of reading in an address when an execution unit 2 is executing some task, a logic circuit 9 calculates logically the corresponding bit of a table identifier 3 and a task identifier 4, decides whether table information set onto a conversion table 1 at present belongs to the task which the execution unit 2 is executed at present or not, and sends a trap signal to an instruction sequencer 5 only when an updating processing of the table information is necessary. In the case the trap signal from the logic circuit 9 is received, the instruction sequencer 5 commands an execution discontinuance of an instruction to the execution unit 2, and transfers the control to the processing for updating the table information. In such a way, a defect which a conventional address converting mechanism such as the updating processing is executed uselessly in spite of a fact that it is unnecessary to execute the updating processing of the table information can be eliminated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an address translation mechanism for an information processing device.

[Conventional technology]

When a task is executed using a virtual storage device on the central processing unit of an information processing device, the address of data or instructions is
Address translation is performed from each virtual memory address to a real memory address. This address translation is performed based on the table information on the translation table, so if multiple tasks are to be executed, multiple pieces of table information are usually required.

If address translation is to be performed while a certain task is currently being executed, identify whether the table information currently set on the translation table is for the task currently being executed,
If it does not belong to the task currently being executed, the table information must be updated to that of the task currently being executed.

Therefore, the address translation mechanism requires a task identifier that indicates the task currently being executed, and a table identifier that indicates which task the table information currently set on the translation table belongs to.

In the conventional address translation mechanism, the contents of the task identifier and table identifier are represented by unique numerical values assigned to each task, and correspond to each task on a one-to-one basis.

[Problem to be solved by the invention]

In the conventional address translation mechanism described above, the contents of one table identifier can only represent one specific task. Therefore, when attempting to use one table information in common among several tasks, if one task When executing this method, there is a drawback that the update processing is executed in vain even though there is no need to update the table information.

[Means to solve the problem]

The address translation mechanism of the present invention is an address translation mechanism that converts a virtual memory address to a real memory address via a translation table on a central processing unit of an information processing device in which a plurality of tasks are executed using a virtual memory device. , task identification means for representing the task being executed in bits; table identification means for representing to which task the table information on the conversion table belongs using the same bits as the task identification means; Compare each bit of the identification means with each bit of the table identification means, and read the table information only when the bit of the table identification means is not set even though the bit of the task identification means is set. and means for transferring control to the updating process.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

When executing an instruction, the execution unit 2 converts the virtual storage address of the instruction or data into a real storage address according to the table information on the conversion table 1. The table identifier 3 indicates to which task the table information currently set on the conversion table 1 belongs, and the task identifier 4 indicates the task that the execution unit 2 is currently executing. Table identifier 3 and task identifier 4 each have the same number of digits (n) as the number n of tasks executed on the central processing unit.
Each bit corresponds to one task. Furthermore, table identifier 3 and task identifier 4 have the same bits and represent the same task.

To which task the table information currently set on the conversion table 1 belongs and which task the execution unit 2 is currently executing is determined by the bits in each digit of the table identifier 3 and task identifier 4 being set to O. It can be expressed by " or 1''.

When the execution unit 2 reads an address while executing a certain task, the logic circuit 9 performs a logical operation on the corresponding bits of the table identifier 3 and the task identifier 4, and calculates the table information currently set on the conversion table 1. , determines whether the execution unit 2 belongs to the task currently being executed, and sends a trap signal to the instruction sequencer 5 only when table information update processing is necessary.

When the instruction sequencer 5 receives a trap signal from the logic circuit 9, it instructs the execution unit 2 to interrupt execution of the instruction, and transfers control to a process of updating table information.

Here, the table information update process means that the instruction sequencer 5 sets the table information dedicated to the task being executed held in the memory 6 into the conversion table 1 from the bus 7 through the bus interface 8, and also sets the table information This is to set table identifier 3 to which task the task belongs.

Next, table identifier 3. The operations of the task identifier 4 and the logic circuit 9 will be explained. Note that the table information updating process after the logic circuit 9 sends out the trap signal is a well-known technique, so a description thereof will be omitted.

First, regarding a certain task, consider the bit representing this task on table identifier 3 and the corresponding bit on task identifier 4. At this time, the necessity of updating the bits of each identifier and the table information is defined as follows.

(1) Regarding the bits of the table identifier.

"1"...Table information belongs to this task.

"o"...Table information does not belong to this task (2) Regarding the task identifier bits.

“1”: Execution unit 2 is executing this task.

"o"...Execution unit 2 is not executing this task.

(3) Regarding the necessity of updating table information.

“'1”: Table information update processing is required.

“o”: Table information update processing is not required.

With this definition, table information update processing is required only when execution unit 2 is executing this task and the table information set on conversion table 1 does not belong to this task. If the task identifier bit is 1'' and the table identifier bit is °“0”
The necessity of table information update processing is "1" only when ', and is "0" in all other cases. The above logical relationship is
It is expressed as shown in FIG. 2(a).

The logical relationship shown in Fig. 2(a) generally indicates that the input is A.
and B, and when the output is X, it can be realized by an AND circuit of negation A and B of input A, as shown in the truth table shown in FIG. 2(b).

In this embodiment, as shown in the logic circuit 9 of FIG. 2, the execution unit 2 is created by associating the output of the table identifier 3 with the input A and the output of the task identifier 4 with the input B. The table information update process is performed only when a task is being executed and the table information does not belong to this task.

Next, think about multiple tasks. In this case, the above-described logical operation is performed individually for all corresponding bits of table identifier 3 and task identifier 4. As a result, when the operation results for all bits are "0", there is no need to update the table information.

However, if the calculation result for any one bit is "1", it is necessary to update the table information, or a trap signal must be sent.

This logical relationship is expressed by the logical sum of the logical operation results for each corresponding bit of the table identifier 3 and task identifier 4 described above, and can be realized by a logical sum circuit such as the logical circuit 9 shown in FIG.

As is clear from the above explanation, table identifier 3. In this embodiment, in which the task identifier 4 and the logic circuit 9 are configured as shown in FIG. , the table information update process is performed only when the execution unit 2 does not belong to the task currently being executed.

〔Effect of the invention〕

As explained above, according to the present invention, the contents of the task identifier and table identifier are represented by one task corresponding to one bit.

Therefore, even if certain table information belongs to multiple tasks, the multiple tasks to which the table information belongs can be represented by setting bits corresponding to those tasks on the table identifier.

Therefore, when the execution unit executes a task, by comparing the contents of the table identifier and the contents of the task identifier, if the table information set on the conversion table does not belong to the task currently being executed, It is possible to update the table information only by updating the table information.

Therefore, it is possible to eliminate the drawback of the conventional address translation mechanism that updating processing of table information is executed in vain even though there is no need to update processing of table information.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the address translation mechanism according to the present invention, and FIGS. 2(a) and (b) are diagrams showing the logical relationship between the contents of the table identifier and the contents of the task identifier in the embodiment of the present invention. It is. 1... Conversion table, 2... Execution unit, 3...
・Table identifier, 4...Task identifier, 5...Instruction sequencer, 6...Memory, 7...Bus, 8...
- Bus interface, 9...logic circuit.

Claims (1)

[Scope of Claim] In an address conversion mechanism that converts a virtual memory address to a real memory address via a conversion table on a central processing unit of an information processing device in which a plurality of tasks are executed using a virtual memory device, task identification means for representing a task in the conversion table with bits; table identification means for representing to which task the table information on the conversion table belongs using the same bits as the task identification means; and the task identification means when reading an address. and each bit of the table identification means, and update the table information only when the bit of the table identification means is not set even though the bit of the task identification means is set. An address translation mechanism comprising: means for transferring control to processing.