JPS6367635A - Microprogram controller - Google Patents

Abstract

PURPOSE:To contrive to simplify the processing method and to increase the processing speed of a microprogram by using the microprogram exclusively for each architecture. CONSTITUTION:A loading control circuit 6 produces the address of a large- capacity memory 7 of a block including a desired microinstruction from an architecture mode held by a register 2 and bits 0-7 of a register 1 and extracts the block out of the memory 7 to load it into a buffer memory 3. In this case, the contents of the register 2 are written to the corresponding entry of an address array 4 together with the contents of bits 0-2 of the register 1. When the block loading action is through to the memory 3, a single word of the memory 3 corresponding to the register 1 is read out to a signal line 11. Then said entry of the array 4 is read out to a signal line 12.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is based on switching architecture modes.
The present invention relates to an information processing device that can operate in a plurality of 7-layer systems, and particularly to a microprogram control device that executes a microprogram loaded from a large-capacity memory into a high-speed buffer memory on the high-speed buffer memory.

(Prior Art) When a plurality of virtual computers are operated on one real computer, each virtual computer is often constructed with a different architecture or technology.

In such cases, the functional differences between these different architectures are often not very large.

As a precaution, it is common practice to determine the architecture mode in which a microprogram is being executed based on these functional differences, and to provide functions in line with each architecture mode.

(The opening/closing point that the invention seeks to solve) In the method described above, in which a microprogram determines the architecture mode that is being executed, either the machine cycles required to determine the mode directly lead to a decrease in processing performance), or This has the drawback that the program sequence has multiple processing functions, which makes the microprograms multiple and increases design errors.

An object of the present invention is to eliminate the above-mentioned drawbacks by dedicating a microprogram to each architecture in a microprogram control device that can operate with multiple architectures, and to avoid having multiple microprograms. The object of the present invention is to provide a microprogram control device.

(Means for Solving the Problems) A microprogram control device according to the present invention includes an instruction register means, a large capacity memory, an address register, a buffer memory, an address array, a comparator, and a load control circuit. It is configured so that it can operate with multiple architectures by switching the architecture mode.

The instruction register means is for indicating the architecture mode currently being executed.

Mass memory is for storing microprograms.

The address register is for the microinstruction address array.

The buffer memory consists of a plurality of blocks that hold part of a microprogram in block units.

The address array has an entry corresponding to each block of the buffer memory, and each entry is for holding a portion of a microinstruction address and an architectural mode.

The comparator inputs the currently executing 7-1000 texture mode, part of the contents held in the address register, and the output of the address array, and checks whether the buffer memory holds the microinstruction to be executed. It is meant to be done.

The load control circuit is for controlling the loading of blocks containing microinstructions from the large capacity memory onto the buffer memory block by block when the microinstructions to be executed are not held in the pack memory. It is.

(Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a microprogram control device according to the present invention. The embodiment shown in FIG. 1 is realized by comprising a register 1, a register 2, a buffer memory 3, an address array 4, a comparator S, a load control circuit 6, and a large capacity memory 7. .

The microprogram in this example is! 16.884
Based on the word capacity, it is divided into four groups each consisting of 4.096 words. In FIG. 1, register ] is a register for holding a 12-bit microinstruction address, register 2 is a 2-bit register for holding the architecture mode being executed, buffer memory 3 is a memory with a capacity of 512 words, Address array 4 is a memory with 82 entries. Buffer memory 3 is 32 times every 16 words.
It is divided into blocks, each block corresponding to each entry of the address array 4.

Buffer memory 3 is given bits 3-1 of register 1 as an address, and address array 4 is given bits 3-7 of register 1 as an address. Each entry of the address array 4 stores the group to which the microinstruction held in the corresponding block of the buffer memory 3 belongs and bits 0 to 2 of the microinstruction address within that group.

Comparator S compares the output of address array 4 with bits 0-2 of register 1 and the output of register 2. Koi
Accordingly, it is detected whether the microinstruction corresponding to the microinstruction address held in register 1 to be executed under the architecture mode held in register 2 is held in buffer memory 3 or not.

When the buffer memory 3 does not hold a necessary microinstruction, the load control circuit 6 is a control circuit that takes out the desired microinstruction from the large capacity memory 7 and loads it into the buffer memory 3. The large-capacity memory 7 is a memory that includes an area for storing 16,884 words of microprograms, and the microprograms stored on the large-capacity memory are divided into four groups corresponding to 4,096-word architecture modes. Each group is further divided into 256 blocks of 16 words.

Next, the operation of this saturation example will be explained step by step.

First, when a microinstruction address is set in register l, one word of the corresponding buffer anomaly 3 is set to the signal line]
1, one entry of address array 4 corresponding to the contents of register l is read out to signal line 12, and the architecture mode currently being executed and the bit of register 1 held in register 2 by comparator 5 are read out. 0-2
compared to If these results match, the information on signal line 11 is validated and the next microinstruction address is set in register l.

However, if the comparison results do not match, the desired microinstruction is not held in the packer memory 3, so the information on the signal line ll is invalidated, and the information on the signal line 11 is sent to the load control circuit 6 via the signal line 13. is activated.

The load control circuit 6 generates an address on the large-capacity memory 7 of a block containing a desired microinstruction from the architecture mode held in the register 2 and bits 0 to 7 of the register 1, and transfers the block to the large-capacity memory 7. 7 and load it onto the pack memory 3. At this time, at the same time, the corresponding entry of address array 4 has register 2.
The contents of bits θ to 2 of register 1 are written.

When the block loading operation to the buffer memory 3 is completed, one word of the buffer memory 3 corresponding to the register 7) is read out to the signal line 11, and the corresponding entry of the L/7° array 4 is successively read out to the signal line 12. The output of address array 4 is compared with the contents of register 2 and the values of bits 0 to 2 of register 1 by comparator 5, and since the comparison results match, output signal line 11 is valid. The next microinstruction address is set in register 1.

(Effects of the Invention) As explained above, according to the present invention, in a microprogram control device that can operate with a plurality of architectures, by dedicating the microprogram to each architecture, the microprogram can be processed at high speed. transformation,
This has the effect that it is possible to achieve simplification and simplification.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a microprogram controller according to the present invention. 1.2...-Register 3φ...Buffer memory 4 pairs...Address array 5...Comparator 6...Control circuit...Large capacity memory Patent Question Ceremony NEC Corporation

Claims (1)

[Claims] an instruction register means for instructing the architecture mode currently being executed; a large capacity memory for storing a microprogram; an address register for holding a microinstruction address; and a part of the microprogram in blocks. a buffer memory consisting of a plurality of held blocks; an entry corresponding to each block of the buffer memory; each entry includes an address array for holding part of a microinstruction address and an architecture mode; a comparator for inputting the architecture mode being executed, part of the contents held in the address register, and the output of the address array, and checking whether or not the microinstruction to be executed is held in the buffer memory; , a load control circuit for controlling to load a block containing the microinstruction from the large capacity memory onto the buffer memory block by block when the microinstruction to be executed is not held in the buffer memory; A microprogram control device comprising: a microprogram control device configured to be able to operate in a plurality of architectures by switching the architecture mode.