JPS60173633A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To decrease program step numbers by operating a storage means storing the state of result of operation of information in the same way as in a general-purpose register. CONSTITUTION:It is considered that an instruction setting a content of an address L+1 ([5] is stored in an address L+1) exists in a condition code register CCR3 of an address L and an instruction adding a value of a register A in a general-purpose register group and a value of the CCR3 and storing the result to the register A exists in an address L+2. The value of a memory data register 9 to which the content of the address L is outputted on an internal bus and the value is set to the CCR3 succeedingly. Then the content L+2 of a program counter 5 is set to a memory address register 8 succeedingly, the corresponding instruction is set to the memory data register 9 and then an instruction register 6 and analyzed by a decoder 7. Then the values of the register A and the CCR3 in the general-purpose register group are added by an arithmetic logical operating device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an arithmetic processing device that enables reading and writing by a program to a holding means that holds the state of the operation result of information.

[Prior Art] In a conventional arithmetic processing unit (hereinafter referred to as CPU), for example, a condition code register (hereinafter referred to as CCR), which holds the state of information operation results, other arithmetic registers, program counters, etc. Unlike the registers, it is not possible to read and write by a program, and it only has a write-during-read means that has many restrictions unique to each CPU.

Types of status include positive, negative, zero, overflow, and
Occurrences of carries are common, and other CPU-specific factors may be added, but these are only automatically rewritten according to the results of each operation, and they must be cleared individually. That's all I could do.

[Objective] The present invention has been made in view of the above-mentioned points, and its object is to provide an arithmetic processing device that can read and write arbitrary information to a holding means that holds the state of information operation results using a program instruction. [Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

The figure is a functional block diagram of an arithmetic processing device according to an embodiment of the present invention, in which 1 is a general-purpose (arithmetic) register, 2 is an arithmetic logic unit, 3 is a condition code register (OCR), 4 is a control circuit, 5 is a program counter that stores the storage location of instructions; 6 is an instruction register; 7 is an instruction decoder that analyzes instructions in the instruction register 6; 8 is a memory address register; 9 is a memory data register; 10 is an internal bus. .

Further, 13 is a memory control circuit, and 14 is a memory.

The information processing process of the arithmetic processing device shown in the figure will be explained below.

An arithmetic processing unit must execute different operations depending on the content of information, and therefore there are cases where the result of one command operation is stored and the next command to be executed is later changed based on that result. Therefore, the CCR 3 is provided to hold the state of information operation results (such as the results of operations in the arithmetic and logic unit 2). Conventionally, it was possible to read the contents of many CCs and R3s, but there were very restrictions on rewriting the contents.
Only bit-only ON10FF was possible.

However, in the non-embodiment, the 0CR3 and the internal bus 1O are connected, and reading/writing can be performed under the control of the control circuit 4 in exactly the same way as in the normal general-purpose register group 1. Also, the information operation result is automatically held in the same <CCR3.

Device of this embodiment 6. The operation will be explained in detail by taking as an example the operation when executing the command shown below.

L MOVI CCR, 5 L+2 ADD AR, OCR Here, "L", "L+2°" indicates the address of the memory 14 where the instruction is stored, and the CCR3 at address "L''
An instruction to set the contents of address "'L+1" (in this case, "°5°" is stored at address L+1) is sent to address "'L+2", and a This shows an instruction to add the value of the register and the value of CCR3 and store the result in the A-register.

When the programs are executed sequentially and the value of the program counter 5 becomes "L", first the value of the program counter 5 is changed to "L" in order to read the instruction from the "L" address of the memory 12.
"' is set in the memorization register 8, this value is given to the memory control circuit 13, and the control circuit 4 instructs the memory control circuit 13 to read the stored data,
When the contents of address L” are read, this value is set in the memory data register 9. Then, the program counter 5
Increase the value by +1. As a result, the value of the program counter becomes °'L+1'''.

The instruction read into the memory data register is immediately set in the instruction register 6 and analyzed by the instruction decoder 7. Here, the contents of the following address "L + 'l°" are set to 0.
Since this is an instruction to be transferred to CR3, the value (L+1) of the program counter 5 is set in the memory address register 8, and in accordance with the memory read request from the control circuit 4, the value (L+1) is
The value stored at address °', ie, 5'' is set in the memory data register 9. The value of the program counter is then incremented by 1 and becomes 'L+2'.

This means that all pre-processing preparations for this instruction have been completed, and the value of memory data register 9 is transferred to internal path 10.
Then, set this to CCR3. These series of controls are performed by the control signal it (indicated by the broken line) from the control circuit 4. This process is simply a transfer process of information, and there is no change in the state of the operation result and no change in the condition code. In other words, CCR3 The content of the program counter 5 remains “5''.Then the content of the program counter 5 is “L+2”.
' is set in the memory address register 8, the corresponding instruction is set in the memory data register 9, and the value of the program counter 5 is incremented by 1.

The value of this memory data register is the command register 6.
is set and analyzed by the instruction decoder 7. Since the values of the A-register and CCR3 are added here, the value of the A-register in the general-purpose register group l is sent to one side of the arithmetic and logic unit 2, and at the same time, the value of CCR3 is sent to one side of the arithmetic and logic unit 2 via the internal bus 10. 2, both values are added, and the addition result is set in the A-register of general-purpose register group 1 via internal bus 10. The control for reading the value of this register, the activation of addition by the arithmetic and logic unit 2, and the control for setting the result in the A-register are executed by a control signal from the control circuit 4 based on the analysis result of the instruction decoder 7.

Further, the state of the result generated by the execution of this instruction, for example, the state of the operation result (■, negative, zero, overflow, carry) is set in OCR,3. This is indicated by the dashed line 12.

As explained above, the state of the operation result is finally set in CCR3, but during that time it can be treated exactly the same as one general-purpose register group.

Also, for the instruction from address L, it is important to set 0CR3 to 5'' or to set 0'' to this 0CR3.
3 can be reset with one command.

This is compared to the case where positive and negative flag bits, zero flag bits, overflow and carry flag bits, etc. must be reset independently (in other words, in three separate steps) during initial settings for arithmetic processing, etc. As a result, significant simplification can be achieved.

[Effects] As explained above, according to the present invention, it becomes easy to operate the holding means that holds the state of the operation result of information in the same way as a general-purpose register, and by increasing the number of general-purpose registers by one, This reduces the number of program steps in a small arithmetic processing unit that must manage limited registers, and speeds up processing.

Furthermore, since any value can be set, initial settings before execution of arithmetic processing can be performed with a single command, and an arithmetic processing device that can simplify programming and improve efficiency has been realized.

[Brief explanation of the drawing]

The figure is a functional block diagram of an arithmetic processing device according to an embodiment of the present invention. In the figure, l...General purpose register group, 2...Arithmetic logic unit, 3...CCR14...Control circuit, 5...Program counter, 6...Instruction register, 7...Instruction Decoder, 8...Memory address register, 9...
Memory data register, 13...Memory control circuit, 1
4...Memory.

Claims (1)

[Claims] An arithmetic processing device comprising: a holding means comprising an input system for the operation results from means for manipulating information and generating the results; and an input system from a data transfer path different from the input system. An arithmetic processing device characterized in that data from the data transfer path can be independently input to the holding means or output to the data transfer path according to a program instruction.