JPS5969843A - Controlling method of microprogram - Google Patents

Abstract

PURPOSE:To shorten the bit length of a microinstruction by holding control information for a block to be processed and control information to be used in common at the process of execution of the microinstruction in a block in an address array. CONSTITUTION:The address of a microinstruction to be executed is set up in the 1st register 1. In accordance with the address set up in the 1st register 1, a microinstruction stored in a buffer memory 2 is read out to the 2nd register 3. Simultaneously, a corresponding entry is read out from an address array 4 and control information to be used in common in a block including the microinstruction is set up in the 3rd register 5. An address comparator 6 discriminates whether the microinstruction read out from the buffer memory 2 is to be executed or not, and when the microinstruction is to be executed, set up the status of an FF 7 to logical ''1''. Consequently, the FF 7 indicates that the data stored in the registers 3, 5 are effective to a decoder 8. Receiving the indication, the decoder 8 operates and executes the microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the Technical Field to which the Invention Pertains) The present invention relates to a microprogram control method in which a part of a microprogram loaded from a large capacity memory into a buffer memory is executed on the buffer memory.

(Description of Prior Art) The information contained in one word of a microinstruction includes a lot of information that is originally used only in some microinstructions. For example, an arithmetic processing unit (ALU: Ar
Binary arithmetic operation functions, decimal arithmetic operation functions, logical operation functions, etc. can be defined in the operation specification of ithmetic and LogicUnit), but each function does not have to be usable in all microprograms. In other words, if the entire microprogram is divided into multiple blocks based on the number of words, each block is configured so that it can realize at least one of the three functions of the arithmetic processing unit. good.

Focusing on this point, Japanese Patent Application No. 54-152664 proposed a method in which the bit length of microinstructions was shortened by providing one decode mode for each block of control memory and placing a decode mode memory to hold these modes. It is proposed in the microprogram control device described.

On the other hand, with the diversification of functions of information processing devices and demands for improved performance, the capacity of microprograms is increasing day by day. However, increasing the size of the control memory to meet these demands increases machine cycles and equipment costs, resulting in a substantial performance drop. As one solution to this problem, a microprogram control system has been proposed in Japanese Patent Application No. 1596/1983, in which a low-cost large-capacity memory and a high-speed buffer memory equipped with an address array are provided.

However, these microprogram control devices and microprogram control methods have the disadvantage that the amount of hardware is still large because the address array does not contain information corresponding to the contents of the decode mode memory.

(Detailed Description of the Invention) The object of the present invention is to provide a microprogram control device described in Japanese Patent Application No. 54-152664, and a microprogram control device described in Japanese Patent Application No. 57-1.
The above drawbacks of the microprogram control method described in No. 596 are solved, and management information for the block to be processed and control information commonly used in the process of executing microinstructions within the block are stored inside the address array. It is an object of the present invention to provide a microprogram control method that can be realized by holding the bit length of a microinstruction and reducing the size of a control memory.

(Description of structure and operation of the invention) The microprogram control method according to the present invention includes the first to third
registers, buffer memory, address array,
address comparator, flip-flop, decoder,
This is realized by having a large capacity memory.

The first register is for holding the address of the microinstruction, and operates as an address register. The buffer memory temporarily stores part of the microprogram in blocks. The second register is for holding microinstructions read from the buffer memory and operates as a microinstruction register.

The address array holds block management information for the microprogram stored in the buffer memory and control information commonly used in the process of executing microinstructions in blocks, and corresponds to each block in the buffer memory. This is the one that has the entry. The third register is for holding control information read from address play and operates as a control register. The address comparator compares the contents of the first register with the block management information to detect whether or not the expected microinstruction exists inside the buffer memory. In the flip-flop, if the address comparator indicates a match and the corresponding microinstruction is present in the buffer memory, state 1 is set, and if A indicates a match, state 0 is set. The state of the flip-flop in the decoder is 1
It operates only when the system decodes the contents of the second and third registers and sends necessary control signals to each control section inside the system. Large-capacity memory is a memory that is made up of a plurality of blocks and is used to hold microprograms, and each block contains corresponding control information.

EXAMPLES Next, the present invention will be explained in more detail with reference to the drawings.

An embodiment of the microprogram control system according to the present invention includes first to third registers 1, 3.5, and a buffer memory 2.
, an address array 4 , an address comparator 6 , a flip-flop 7 , a decoder 8 , and a large-capacity memory 9 .

In FIG. 1 showing an embodiment of the present invention, a first register 1 is an address register for holding the address of a microinstruction, and a buffer memory 2 blocks a part of a microprogram read from a large capacity memory 9. The second register 3, which is a memory for holding in units, is a microinstruction register for holding microinstructions read out from the buffer memory 2. The address array 4 holds block management information for the microprogram stored in the buffer memory 2 and control information commonly used in the process of executing microinstructions within the block. It has an entry corresponding to each block. The third register 5 is a control information register for holding the control information read out from the address array 4. The address comparator 6 compares the block management information read from the address array 4 with the first register 1.
It uses part of the microinstruction address held in the buffer memory 2 to detect whether or not the expected microinstruction exists inside the buffer memory 2, and if it does, the state of the flip-flop 7 is set to a logical value. This is a comparator for setting the state of the flip-flop 7 to logic value 1 if present. The decoder 8 inputs the contents held in the second register 3 and the third register 5, and when the state of the flip-flop 7 is 1, it is a decoder for sending a control signal to each control unit in the system. . The large capacity memory 9 is made up of a plurality of blocks and is a memory for holding microprograms, and includes control information corresponding to each block.

Hereinafter, the operation of this embodiment will be explained step by step according to FIG. First, the address of the microinstruction to be executed is
Set to register 1 of

Next, the microinstruction inside the buffer memory 2 is read out to the second register 3 in accordance with the address set in the first register 1. At the same time, the corresponding entry is read from the address array 4 and the control information commonly used within the block containing the microinstruction is stored in the third register 5. At the same time, the address comparator 6 determines whether the microinstruction read from the buffer memory 2 is to be executed.

If this microinstruction is to be executed, set the state of flip-flop 7 to logic value 1,
It indicates to the decoder 8 that the data held in the first register 3 and the second register 5 are valid. Upon receiving this, the decoder 8 sends a control signal to each control unit in the system, calculates this microinstruction, and executes processing. If the above-mentioned read microinstruction is not to be executed, the state of the flip-flop is set to a logical value of 0, and the data in the first register 3 and the second register 5 are invalidated to the decoder 8. Indicates that At the same time, the large capacity memory 9 is instructed to access the microinstruction address held in the first register 1 and load a block containing the corresponding microinstruction. The large-capacity memory 9 sequentially stores all microinstructions in the above block.
The control information and block management information commonly used by the microinstructions inside the block are written into the corresponding entry of the address array 4 as well as into the corresponding block of the buffer memory 2. When the above process is completed, 1. The address held in the first register 1 is accessed again, the corresponding contents of the buffer memory 2 are read out, and the contents are set in the second register 3. Along with this,
The corresponding entry in the address array 4 is read and the above control information is set in the third register 5. At this time, the block management information read together with the control information is the content written in the block load operation described above, and as a matter of course, the address comparator 6 uses the data read from the buffer memory 2 to execute the block management information. It is determined that it is a microinstruction, and the state of the flip-flop 7 is set to logical value 1. As a result, the flip-flop 7 instructs the decoder 8 that the data held in the first register 3 and the second register 5 are valid. The decoder 8 receives these, sends control signals to each control section inside the system, and calculates and executes the microinstructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a device for implementing the microprogram control method according to the present invention. 1.3.5...Register 2...Buffer memory 4...Address array 6
...Address comparator 7...Flip-flop 8 River decoder 9...Large capacity memory patent applicant NEC Corporation

Claims (1)

[Claims] A first register for holding the address of a microinstruction, a buffer memory for temporarily storing a part of the microprogram in blocks, and a first register for holding the microinstruction read from the buffer memory. 2
registers, block management information of the microprogram stored in the buffer memory, and control information commonly used in the microinstruction execution process in units of blocks, and is stored in each block of the buffer memory. an address array having corresponding entries; a third register for holding the control information read from the address array; and an address for comparing the contents of the first register and the block management information. a comparator, a flip-flop for setting a state 1 if the address comparator indicates a match and a state 0 if the address comparator does not indicate a match; A decoder for decoding the contents of the second and third registers and outputting a control signal only when A microprogram control system characterized by being equipped with a special memory for storing only a few items.