JPH0277935A - Line buffer memory - Google Patents

Abstract

PURPOSE:To attain the simultaneous performance of both reading and writing actions for improvement of the time conversion efficiency and at the same time to facilitate an editing job by using two memories of the toggle constitution, an address setting register, a read counter, etc. CONSTITUTION:A RAM(A) 8 and a RAM(B) 9 perform the toggle actions and either one of these two RAMs is set in read state while the other is kept in a write mode. Then the action switching timing, i.e., an address is previously set at an address setting register 12 so that the RAM 8 or RAM 9 is changed to a read state from a write state and vice versa. Thus an interruption signal is generated when the switch timing is set via a read counter 11 and a comparator 13. Then a toggle signal is requested to a controller, and the controller produces a toggle signal 6. Thus the memory actions are switched between both RAM 8 and RAM 9. As a result, both reading and writing actions can be performed at one time for improvement of the time conversion efficiency. Furthermore a data editing job is facilitated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a line buffer memory that efficiently performs time conversion of data (frequency of A - frequency of B) and that allows easy data editing. .

[Conventional technology]

Figure 3 shows a conventional device that performs time conversion of data, which is necessary when displaying an image created by a microcomputer (hereinafter referred to as microcomputer) on an image display device at a constant rhythm. This is a diagram showing an example of the configuration, and shows what is generally called a dual port RAM.In the diagram, 1 is an input terminal to which an input signal is connected, and 2 is an output terminal to which a time-converted output signal is output. , 4 is a write clock (for example, a microcontroller's CPU, M
Terminal 5 is a terminal that applies a read clock that is the rhythm required after conversion (for example, the rhythm of an image display device that is a peripheral device of the microcomputer ÷). Also, Figure 4 shows the 3rd
FIG. 2 is a timing diagram for explaining the operation of the device shown in FIG.
100 is data stored in the RAM 17.

Next, the operation of the apparatus shown in FIG. 3 when data generated at a frequency of, for example, 1 kHz is converted to 2 kHz will be described.

First, as shown in FIG. 4(a), when a 1 kHz write clock is applied to the write clock input terminal 4 and write data is applied to the input terminal 1, data is sequentially written from address 0 of the RAM 17 in synchronization with a 1 kHz cycle. 0, where write data is stored, shows an example in which 4-bit data "0110" is stored from address 0 to address 3.

On the other hand, as shown in Figure 4), during readout, the frequency is 2kHz.
When the read clock is applied to the read clock terminal 5, the data stored in the RAM 17 is sequentially read out from address 0 of the RAM in synchronization with a 2 kHz cycle. In the figure, from address 0 to address 3, 4-bit data “0110
'' is read out in order.

[Problem to be solved by the invention]

Conventional devices that perform time conversion of data are configured as described above, so if writing is performed at the same time as reading, the data being read may be destroyed, so reading and writing are performed sequentially (one write, one read, one Write-)
There is a problem in that the efficiency of time conversion deteriorates because reading and writing cannot be performed simultaneously.

The present invention has been made to solve the above-mentioned problems, and aims to provide a line buffer memory in which reading and writing can be performed simultaneously, time conversion can be performed efficiently, and data can be easily edited.

[Means to solve the problem]

The line buffer memory according to the present invention is A.

Using 82 memory areas, a toggle method is adopted in which when A (B) is in the write state, B (A) is in the read state,
There are two memory operation switches in advance in the address setting register (A (B) is from the write state to the read state,
Set the timing (address) for B (A) to change from the read state to the write state, and when information is read from memory B (A) in the read state to the set address, a toggle signal is activated. It is designed to generate an interrupt signal for making a request.

[Effect]

In this invention, A uses 82 memory areas,
When A (B) is in the write state, B (A) is set to be in the read state, and the timing for the toggle operation is set in advance in the address setting register, and when the timing is reached, the controller such as the CPU, MPU, etc. Generates an interrupt signal to set the timing of toggle operation.
By notifying a controller such as a PU or MPU, this controller generates a toggle signal and performs the toggle operation, making it possible to perform reading and writing at the same time.

〔Example〕

FIG. 1 is a configuration diagram showing a line buffer memory according to an embodiment of the present invention. In the figure, 1 is an input terminal to which an input signal is connected, 2 is an output terminal to which a time-converted output signal is output, and 3 is an output terminal to which a time-converted output signal is output. is CPU.

An interrupt terminal outputs an interrupt signal to request a toggle signal from a controller such as an MPU, and 4 is a write clock (for example, a controller such as a microcontroller's CPU or MPU) for writing the input data that becomes the rhythm before time conversion into the RAM. 5 is a terminal that applies a read clock that becomes the rhythm required after conversion (for example, the rhythm of an image display device that is a peripheral device of the microcomputer mentioned above), 6 is a terminal that applies a read clock that changes the state of the RAM. 7 is an address setting terminal for setting the read range, 8 is RAM (A), 9 is RAM (B), 10 is a write counter that indicates the RAM address at the time of writing, 11 is a read counter that indicates the RAM address at the time of reading, 12 is an address setting register for storing the reading range, and 13 is a read counter 1.
A comparator that compares the value of 1 with the value of the address setting register 12 and generates an interrupt signal when they match; 14 is a selector that distributes input signal 1 to RAM (A) 8 or RAM (B) 9; 15 is a write clock 4 Or a selector that distributes the read clock 5 to RAM (A) 8 or RAM (B) 9, 16 is RAM (A) 8 or RAM
This is a selector that determines which data of M(B)9 is to be output.

FIG. 2 is a timing chart for explaining the operation of the device in FIG. 1, and 101 and 102 are RAM
This is the data stored in (A) and (B). In this figure, for simplicity, RAM (A) is used.

(B) Writing is 4 bits, reading is 3 bits,
The writing and reading clock frequencies are shown as being the same.

First, RAM (A) is set to the write state, and the information “0110” input to input terminal 1 is written to addresses 0 to 3 of RAM (A) in synchronization with write clock 4 (second (a)), at that time, RAM (B) is set to the read state and the RAM (B) is read out in synchronization with the read clock 5.
The information written in addresses 1 to 3 of (B) “10
0" is output to output terminal 2. In this example, start address 1 and stop address 3 are set in address setting register 12, and read counter 1
When 1 selects "3" at address 3, the comparator 13 generates an interrupt signal 3 and requests a toggle signal from a controller such as the CPU or MPU. In response to this, the controller generates a toggle signal 6 ((bl) in the same figure).

The toggle signal 6 puts the RAM (A) into the read state, and among the information "0110" previously written in addresses 0 to 3 of RAM (A), addresses 1 to 3 set in the address setting register 12 are read. The information @110'' up to address 3 is output to output terminal 2 in synchronization with read clock 5, and when address 3 is read out, interrupt signal 3 is generated as before ((C) in the same figure).

Note that RAM (B) is in a writing state at that time, and in this example, information “0011” is written (see (d) in the same figure).
)).

In such a device, there is no risk of data destruction even when reading and writing are performed simultaneously, time conversion can be performed efficiently, and data can be easily edited.

In addition, in the above embodiment, RAM (A), RAM (B)
have been described as data memory areas each having a width of 1 bit, but this is a data memory area having a width of multiple bits (for example, I BYTII!).
It may be a data memory area (TE=8 bits), or it may be a RAM or a static RAM.

Further, in the above embodiment, writing is performed in synchronization with the "L" → "H" clock, and reading is performed in synchronization with the "H" → "1L" clock.
Further, although the case where the write clock 4 and the read clock 5 have the same frequency has been shown, these clocks can be freely selected, and whichever clock is faster can be used without any problem.

Furthermore, in the embodiment described above, both the start address and stop address for reading are set in the address setting register 12, and the interrupt signal 3 is generated when the read counter value reaches the stop address. There is no problem in specifying only one of them, and there is no problem in setting it freely, such as outputting interrupt signal 3 when the read counter value reaches the start address.

〔Effect of the invention〕

As described above, according to the line buffer memory according to the present invention, the two memories have a toggle configuration, and by setting the readout area in the register, only the necessary range is read out, and after the readout of the necessary area is completed, the controller Since an interrupt signal requesting a toggle signal is generated, editing is easy and time conversion can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a line buffer memory according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, FIG. 3 is a configuration diagram showing a conventional dual port RAM, and FIG. 4 is a timing diagram for explaining the operation. 3 is an interrupt terminal, 4 is a write clock terminal, 5 is a read clock terminal, 6 is a toggle terminal, 8 is a RAM (A)
, 9 is RAM CB), 12 is an address setting register, and 13 is a comparator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a line buffer memory that performs time conversion of data, two memory areas are set in which one is set to a write state and the other is set to a read state, and the address at which the state of the above two memory areas should be switched is set. and means for generating an interrupt signal for requesting a toggle signal for performing the switching when information is read from the memory area in the read state to the set value of the register. and line buffer memory.