JPS60193044A - Data buffer device - Google Patents

Abstract

PURPOSE:To always comply with read request and to improve the data transfer efficiency by storing a prescribed data number to one of both buffer memories and at the same time giving the write control to the other buffer memory. CONSTITUTION:The data given from an input line 101 are written successively to either one of buffer memories 1 and 2 with the control given from buffer control circuits 9 and 10 respectively and according to the addresses designated by buffer address counters 3 and 4. The circuit 9 monitors the value of the counter 3 via an input line 302 and discontinues a writing action when the value of the counter 3 reaches a set level and gives an indication to the circuit 10 through an output line 902 to write the data to the memory 2. The memory 1 receives a read request and reads out stored data at and after an address ''0''.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data buffer circuit, and particularly to a data buffer circuit that uses two RAMs.
The present invention relates to a data buffer circuit that is capable of stopping a write operation at a particular address and reading it out in a data buffer having a double buffer configuration using the above.

[Prior art]

Data buffer circuits for controlling transfer speeds are often used between systems and devices that generally exchange data in an asynchronous manner, such as between a computer system and a peripheral device. In such cases, data transfer is generally performed using the system bus or at a higher speed than the data bus, and the data received via the system bus is stored in a data buffer and then sequentially sent to the device. Alternatively, the data received from the device side may be stored in a data buffer and then sequentially sent to the system bus, so that the data transfer is performed while buffering the difference in transfer speed between the bus twins with the data buffer. It is well known that

Data buffers used for this purpose are usually F
There are methods that use buffer memory or registers based on the IFO (First-In-First-Out) method, and methods that use RAM, but among these, those that use RAM have a simple configuration and a relatively small shape. Although it is often used for reasons such as miniaturization, it is not possible to increase the depth of 1 in, total, and out at the same time. They are often combined.

However, due to power reasons, in this double buffer configuration data buffer circuit that uses two RAMs, the data buffer circuit uses two RAMs.
There is a restriction that data cannot be loaded into the other RAM until one of the two RAMs has been completely written.
For this reason, even if a read request is received before the writing to the RAM is completed, this service cannot be answered, and this tendency is particularly noticeable at the start of data transfer, which is a drawback.

[Purpose of the invention]

The purpose of the misfiring Q'J is to eliminate the above-mentioned drawbacks and to
In a data buffer device configured with M as a buffer memory, at the start of data transfer, when a predetermined number of data is stored in one of the buffer memories, write control is passed to the other buffer memory, and the device itself enters a read waiting state. ,
After that, even if the buffer memory being written to does not reach the write completion state, as soon as the valid data in the buffer memory being read reaches 1″0#, the writing operation can be stopped at the address at that point and the read operation can be started. It is an object of the present invention to provide a data buffer device which can stop writing to a buffer memory at an arbitrary address and respond to a read request even if it is in the middle of writing to a buffer memory.

[Structure of the invention]

The device of the present invention includes a memory circuit having a plurality of data storage locations, and a memory circuit that specifies the data storage location of this mesori circuit and updates the contents so as to designate the next data storage location when writing and reading operations for the memory circuit are completed. An address counter, an address register that holds the data storage position in the address counter in the previous write operation, and a read operation that compares the contents of the address counter and the address register to detect the presence or absence of valid stored data in the memory circuit. and a flip-flop circuit that is set at the start of data transfer and reset by one of the memory control circuits. In the buffer device, when the flip 7 four-tube circuit is set at the start of data transfer, either one of the two buffer means executes a write operation, and the address counter during the write operation is set in advance. When the value reached, the buffer control circuit during the write operation stops the reading operation and resets the 7 lip-flop circuits, and at the same time causes the other buffer 7 means to start the write operation and shifts the continuous write operation to the depth. After that, the two buffer means alternately carry out the writing and reading operations, while the buffer means that performs the write operation uses the effective stored data detection circuit of the buffer means that performs the read operation. The data writing/reading means is configured to be capable of stopping the writing operation and then shifting to the reading operation even if the address of the memory circuit has not reached the highest address when no data is detected.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment shown in FIG. 1 includes buffer memories IJ (1) 1 and (2) 2 which constitute a double buffer using RAM, buffer address counters α) 3 and (2) 4 which have the same functions, respectively. Buffer address registers (1) 5 and (2) 6, comparators α) 7 and G2) 8, balance control circuit (1)
) 9 and (2) 10, a selector 11, and a 7 ripple 7' drop circuit 12 for instructing the start of data transfer.

Data supplied via the input line 101 is written into either the buffer memory lj (1) 1 or (2) 2, and this write operation is performed by the buffer control circuit α) 9.
and output cash input 301 from buffer address counter (1) 3 or (2) 4 under the control of 0) 10.
Alternatively, it is executed one after another for the address specified via 401 as follows.

Buffer address counters (1) 3 and (2) 4 all have count values at the time of initial setting that are all composed of binary logical values "'0", and buffer address registers (1) 5 and The registered values of the buffer address 7 register C2)6 are all set to ``1'' at the time of initial setting.These buffer address counters and buffer address registers are set to the buffer address α)1 and buffer memory 0).
Each time input data is written to 2, the buffer address counter increments by 1, and while writing to the corresponding back memory, the buffer address register inputs and monitors the count value of the buffer address counter. Also, during reading, it is controlled to hold the final write address value, that is, the previous value of the buffer address counter.For example, if the count value of the buffer address register is 3, the contents of the buffer address register are held at 2. The registered value is set in this way.

The flip-flop circuit 12 is an indicator indicating whether or not it is time to start data transfer.
phase), the logic value is ``'1'', and the other 7Azes are the logic value 10''. The flip-flop circuit 12 is set to the logic value 61# by a processor (not shown) that is in charge of the entire data transfer. input line 120
1, and the value of the flip-flop circuit 12 is supplied to the buffer control circuit (1) 9 from the output line 12o2. Resetting occurs via output line 904 from buffer control circuit 9.

Buffer control circuits (1) 9 and (2) 10 are buffer control circuits (1) 9 and (2) 10, respectively.
The write/read control in step 2 is carried out as follows.

Initializes buffer address counters 0)3 and C2)4 via output 2 inputs 901 and 1001, and buffer address registers (1)5 and (2)6 via output lines 903 and 1003. Let's do it. Furthermore, the count values of the buffer address counters (1) 3 and (2) 4 are obtained through the input 2 inputs 302 and 402, and when biting, the count values of the buffer memory (1) 1 are obtained.
Or (2) monitor the data storage status in step 2. Further, the outputs of comparators α) 7 and comparators (2) 8 are obtained through output lines 701 and 801, respectively, and it is determined whether the buffer is empty at the time of reading. Furthermore, they can communicate with each other via output lines 901 and 902.

Comparator (1)? and (2) 8 is the buffer address counter α) 3 and the buffer address counter (2)
) 4 and the corresponding buffer address register (1) 5, 7, address register C2) 6, and if they match, the logic value ``''1# is sent to output lines 701 and 801, respectively.

Next is the main dormitory 91! A specific example of the operation of the data buffer device will be explained.

Data transfer is initiated by a control processor (not shown) through input line 1201 to flip-flop circuit 1.
2 is set to logic “1#”, the buffer control circuit (
1) 9 determines that it is the data transfer start phase based on the signal sent from the output line 1202, and writes the data supplied from the input line 101 to the buffer memory (1) 1. The buffer address counter (1) 3 is incremented by 1 every time data is written to the buffer address counter (1) 1. The buffer control circuit (1) 9 monitors the output of the buffer address counter (1) 3 via an input line 302, and when the count value reaches a preset value, stops the write operation and outputs the output via the output 2 input 902. Buffer control circuit (2) 10
Instructs to write the data supplied to memory 0)2, initializes buffer address counter α)3 to all @0#, resets flip-flop circuit 12 via output line 904, and reads out the data. Set to standby state. The write stop value is set in advance based on the data transfer speed difference between the system and the device.

Buffer control circuit +2) 10 writes data supplied from input line 101 into buffer memory (2) 2 in accordance with a write start instruction received from buffer control circuit (1) 3 via output line 902. This instruction to stop writing to the buffer memory is given by the buffer control circuit (2) 10
monitors output line 402 and buffer memory (2)
If it is determined that the data has wandered to the highest address of 2,
Reading of buffer memory 1 (bar 1) 1 is completed and input line 9
It is issued when notification of read completion is received from the buffer control circuit (1) 1 via the buffer control circuit (1) 02.

When a read request is received, the buffer memory (1) 1 reads the stored data from address 0# of the memory.

The count value of the buffer address counter α)3 increases by +1 each time data is read. Buffer address register (1) Holds the write final address value acquired via the output line 302 when S is true when writing.

Comparator α)7 is buffer address register α)
Write final address value held by 5 and output line 303
When it matches the count value received via
That is, when the reading from the buffer memory α)1 is completed and the stored contents of the buffer memory α)1 become empty, the logic 11'' is sent out.

When the buffer control circuit (1) 3 receives this information via the output 2 in 701, it notifies the buffer control circuit G2) 4 of the completion of reading and also starts the buffer address counter (
1) 3 and buffer address registers (1) and 5 are reset to the initial setting values of all "0# and 11" via output 2 inputs 901 and 903 respectively, and are controlled to standby state for write operation to buffer memory (1) 1. do.

When the buffer control circuit (2) 10 receives the reading end instruction, it stops writing even if the highest address of the buffer has not been reached yet and sets the buffer address counter (2) 4 to the initial setting of all 10# via the output line 1003. It is controlled to be in standby state for polishing operation, and the reading service is performed as soon as a measurement request is received. In operation, the buffer control circuit ψ)1
Buffer address counter (2) under control by 0
'i, buffer address register (2) 6 and comparator (2) 8 are carried out in exactly the same way as the read operation described above.

Buffer control scheme (1) 3 performs writing as soon as a write request is received. In this case, since the flip-flop circuit 12 has been reset, the write stop address is the highest address or iG of buffer (2) 2, like the other buffer.
'tlL becomes the address written at the end.

The selector 11 selectively outputs the outputs of these buffer memories and connects them to the output line 1101 so that the data read one after another from the buffer memory (1) 1 or the buffer memory (2) 2 can be output one after another. feed out of the buffer via.

In this way, in a double buffer composed of two RAMs, when data transfer starts, when writing to one buffer reaches a preset address smaller than the highest address, the writing is stopped and control is transferred to the other buffer. When the data is written to one of the RAMs, even if the data write operation in one RAM is not completed, when the other buffer finishes reading, it will stop at the address at that point and store data until then. A double buffer is easily formed that can respond to requests for reading data.

Note that the flip-flop circuit 12 is a buffer control circuit α.
) 9 may be connected to the buffer control circuit Q) 10 instead. In this case, the buffer memory C2)2 is the buffer to which writing is first performed when data transfer is started.

Furthermore, each of the constituent items shown in the embodiment of FIG. 1 can be constructed as a single structure that includes all of them, and it is also possible to construct an arbitrary number of components according to the writer's wishes. it is obvious.

〔Effect of the invention〕

As explained above, according to the present invention, in a data buffer device configured with two R and M double buffer memories, at the start of data transfer, only a predetermined number of data is stored in one of the buffer memories. Then, the write control is passed to the other side and the other side enters the read standby state, and from then on, even if the backup memory in the process of writing is not completely completed, the number of ringing data in the buffer memory in the process of reading is '0'. ”, the write operation is stopped at the address at that point and the data is read out, and the input data is written to the other backup memory by means of which the data is transferred. This has the effect of realizing a data buffer device that can meet the demands and significantly improve data transfer efficiency.

[Brief explanation of the drawing]

FIG. 1 is a four-dimensional diagram showing the central part of the present invention. 1... Buffer memory α), 2... Backer memory (2), 3... Buffer address counter (1) 1.4... Buffer address counter (2), 5...Buffer address register α), 6. Old...Buffer address register (2),
'y... Comparator (1), 8...
Comparator (2), 9...Buffer address counter controller α), 10...Buffer address counter controller (2), 11...
・Selector, 12... Clip-flop circuit.

Claims (1)

[Claims] A memory circuit having a plurality of data storage locations, an address counter that specifies the data storage location of this memory circuit and updates the contents to designate the next data storage location upon completion of write and read operations for this memory circuit, and the previous write. an address register that holds a data storage position in the address counter during operation; and a detection circuit that compares the contents of the address counter and the address register during the start-up operation to detect whether there is a valid storage take in the mesori circuit. a memory control circuit for controlling read/write operations for the memory circuit; and a buffer means having two buffer means each having a trigger flop circuit that is set at the start of data transfer and reset by one of the memory control circuits. In the apparatus, when the flip-flop circuit is set at the start of data transfer, one of the two buffer means executes a write operation, and the distance t' during the write operation is set in advance by the address counter. When the buffer control circuit reaches the end of the write operation, it stops the write operation of the buffer control circuit during the write operation, resets the trigger flop circuit, starts the write operation to the other buffer means, and immediately shifts to the execution of the read operation. After that, the two buffer means alternately carry out writing and reading operations, and the buffer means that performs writing detects the valid stored data of the buffer means that performs read operation. A data write interruption means is provided which can correct the number 1+ operation and shift to a read operation even if the address of the previous IWj memory memory has not reached the highest address when no valid data is detected. A data buffer device characterized by: