JPS5938862A - Memory access system - Google Patents

Abstract

PURPOSE:To operate a storage device without losing an economical property, by sending back a data, etc. accumulated in a data register to a central processing unit, when an address transferred from the central processing unit coincides with accumulated contents of an address register. CONSTITUTION:A storage part MU stores a data, etc. An address register AR accumulates an address a1 transferred from a central processing unit CPU, and a data register DR accumulates a data, etc. extracted from the storage part MU. The address a1 transferred from the central processing unit CPU is collated with accumulated contents a2 of the address register AR by a collating circuit MA, and when the coincidence is detected by this collating circuit MA, the data, etc. accumulated in the data register DR are sent back to the central processing unit CPU. A storage control part MC controls an operation of each part.

Description

DETAILED DESCRIPTION OF THE INVENTION ia) Technical Field of the Invention The present invention relates to a memory access system, particularly a storage device that stores programs and data, and a central processing unit that reads and processes the programs and data from the storage device. This invention relates to a memory access method in a data processing device.

(bl Technology background) With recent advances in semiconductor logic devices, the calculation speed of central processing units has been rapidly improving.On the other hand, the storage density of memory devices has been improving; It falls far short of that.

As a result, the speed of the storage device limits the processing capacity of the data processing device, and there is a strong demand for faster storage devices.

(C) Prior Art and Problems A so-called cache buffer memory method is known as a conventional memory access method designed to increase the speed of this type of storage device. In this method, a small-capacity high-speed memory is installed between the central processing unit and the storage device, and the frequently used data of the central processing unit is stored in advance from the programs and data (hereinafter collectively referred to as data) stored in the storage device. The central processing unit accesses the high-speed memory to increase the speed. However, in this method, not only a high-speed memory is required, but also the frequency of use of the memory contents of the high-speed memory (so-called hint rate) becomes a problem, and when using other than the memory contents, the communication between the storage device and the high-speed memory becomes a problem. A means for exchanging the stored contents by transferring the stored contents at high speed between the two is required, which results in a loss of economic efficiency of the data processing apparatus.

(dl Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional memory access method as described above and to realize a means for increasing the speed of a storage device without impairing the economic efficiency of the data processing device. Ru.

(el) Structure of the Invention The object of the present invention is to provide a data processing device that includes a storage device that stores programs and data, and a central processing unit that reads and processes the programs and data from the storage device. an address register that stores addresses transmitted from the processing device, a data register that stores the data sequentially output from the storage device, an adder circuit that adds 1 to the stored contents of the address register, and the central processing unit. By providing means for determining whether the address transmitted from the device matches the contents stored in the address register, and when it is determined by the means that they match, the data stored in the data register is returned to the central processing unit. achieved.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a memory access method according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the operation process in FIG. 1. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 1, the storage devices include a storage unit MU that stores data, and a central processing unit CPU (not shown).
an address register AR that stores the address a1 transmitted from the address register AR; a data register DR that stores data extracted from the storage unit MU; an adder circuit AD that adds 1 to the stored content a2 of the address register AR; a verification circuit MA that verifies the address a1 transmitted from the processing unit CPU and the stored content a2 of the address register AR;
The storage controller MC includes a storage control unit MC that controls the operation of each of the units. Next, the operation of the storage device will be explained with reference to FIG. In the initial state, the stored contents a2 and dl of the address register AR and data register DR are both O. Now, when address m is transmitted from the central processing unit CPU as address a1 along with the read instruction signal r that instructs the successive operation of the enable signal e1 and the command signal i that instructs the successive command operation, the collation circuit MA is transmitted. Address al=m and accumulated content a of address register AR
2-0 and outputs a mismatch signal n. The storage control unit MC, which has received the mismatch signal n, sends a cent timing signal t1 to the address register AR, and sets the address a1.
is stored in address register AR. As a result, the accumulated content a2 of the address register AR also becomes the address m, and the address m of the storage unit MU is accessed, and the data [(m) (in this case, an instruction) stored at the address m is extracted. Subsequently, the memory control unit MC sends a cent timing signal t2 to the data register DR, and after storing the extracted instruction (m) in the data register DR, the memory control unit MC further sends a cent timing signal t2 to the data register DR.
The drive signal dv is sent to the data register DR, and the stored contents dl=(m) of the data register DR are outputted as output data d2=(m). At the same time, the synchronizing signal S is output via the driver DV2, and the central processing unit CPU is outputted together with the output data [d2-(m).
send it back to Note that the adder circuit AD is an address register A.
1 is added to the accumulated content of R, a2=m, and m+1 is output.

Subsequently, the storage control unit MC sends a set timing signal t1 to the address register AR, and m+l output from the adder circuit AD is accumulated in the address register AR. As a result, the stored content a2=m+l is output from the address register AR, and the storage unit MU is accessed, and the storage unit MU
The next instruction (m+1) is extracted from address m+1. Next, the memory control unit MC sends a set timing signal t2 to the data register DR to store the instruction (m+1> extracted from the memory unit MU. In this state, the next instruction (m+1) is read from the central processing unit CPU. In order to output the address al=m+l, the enable signal e and the read instruction signal r
When the instruction signal i is transmitted together with the command signal i, the collation circuit MA collates the transmitted address al=m+1 with the stored content a2=m+1 of the address register AR, and outputs a match signal y. The storage control unit MC that received the coincidence signal y sends a drive signal dv to the driver DVI, and the data register D
The accumulated contents of R dl=(m+1) are output data d2−(
Output as m+1>. At the same time, the synchronizing signal S is output via the driver DV2, and the output data type c12=(m+1
) is sent back to the central processing unit CPU. Note that the adder circuit AD stores the accumulated contents of the address register AR a2=m+l
1 is added to output m+2. Subsequently, the storage control unit MC sends a set timing signal t1 to the address register AR, and the adder circuit AD is sent to the address register AR.
The output m+2 is accumulated. As a result, the stored content a2-m+2 is output from the address register AR, the storage unit MU is accessed, and the next instruction (m+2) is extracted from address m+2 of the storage unit MU. Subsequently, the storage control unit MC sends a cent timing signal t2 to the data register DR.
, and the instruction (m+2) extracted from the storage unit MU is stored. Similarly, each time the central processing unit CPU transmits successive addresses al=m+2, m+3, . By sending a signal, the accumulated content of data register DR is immediately changed to dl=(m+
2), (m+3), -, etc. are sent back to the central processing unit CPU as output data d2 together with the synchronization signal S.

As is clear from the above description, according to the present embodiment, the storage device has continuous addresses al=
As long as m+1, m+2, m+3, . . . are transmitted, the storage content dl=(m+
1), (m+2), (m+3), . . . are immediately returned to the central processing unit CPU as output data 1ld2. The reading time Tl of data in such a case is halved compared to the reading time T2 when data is extracted from the storage unit MU.

Note that FIGS. 1 and 2 are only one embodiment of the present invention, and for example, a storage device has one set of address registers AR and data for every address a1 transmitted from the central processing unit CPU. The register DR1 is not limited to the addition circuit AD and the collation circuit MA, and one set for instructions and one for data are provided independently, and the reading of the command signal l and data transmitted from the central processing unit CPU is performed. It is also possible to maintain the continuity of the instruction and data read addresses independently by selectively using both sets according to the instructing data signal p, but the effects of the present invention do not change even in such a case. Also, focusing on the fact that there is little continuity in data read addresses, the data address register AR, data register DR1 adder circuit AD, and matching circuit M/A are omitted, and one set of address register AR, data register DR, Although it may be considered to dedicate the adder circuit AD and the collation circuit MA to instructions, the effects of the present invention do not change even in such a case. Further, the means for determining the continuity of the address a1 transmitted from the central processing unit CPU is not limited to the collation circuit MA in the storage device, and the means for determining the continuity of the address a1 transmitted from the central processing unit CPU is not limited to the check circuit MA in the storage device, but also a jump establishment signal indicating the discontinuity of the address a1 from the central processing unit CPU. It is also considered that the storage control unit MC that receives the information makes the determination, but the effects of the present invention do not change even in such a case.

(Phantom) As described above, according to the present invention, in the data processing device,
By providing some mechanisms in the storage device, the time required to read data stored in consecutive addresses can be significantly reduced, and this provides a means to speed up the storage device without impairing the economic efficiency of the data processing device. It becomes possible to realize this.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a memory access method according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the operation process in FIG. 1. In the figure, MU is a storage unit, AR is an address register,
DR is a data register, AD is an adder circuit, MA is a collation circuit, MC is a memory control unit, DVI and DV2 are drivers, al is an address, a2 is the stored content of the address register, dl is the stored content of the data register, and d2 is the output Data type, e is enable/pull signal, r is read instruction signal, W is write instruction signal, i is command signal, p is data signal, S is synchronization signal, tl and t2 are cent timing signals, d
v is a drive signal, y is a coincidence signal, n is a mismatch signal, m, m
+l and m+2 addresses, (m), (m+1) and (
m+2) indicates data type (command). Figure 1'! ! Az diagram

Claims (1)

[Claims] A data processing device comprising a storage device that stores programs and data, and a central processing unit that reads and processes the programs and data from the storage device,
an address register that stores addresses transmitted from the central processing unit in the storage device; a data register that stores the data read from the storage device; and an adder circuit that adds 1 to the contents stored in the address register. and,
means for determining whether the address transmitted from the central processing unit matches the contents stored in the address register; and when the means determines that they match, the data stored in the data register is returned to the central processing unit. A memory access method characterized by: