JPS56163572A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS56163572A
JPS56163572A JP6625880A JP6625880A JPS56163572A JP S56163572 A JPS56163572 A JP S56163572A JP 6625880 A JP6625880 A JP 6625880A JP 6625880 A JP6625880 A JP 6625880A JP S56163572 A JPS56163572 A JP S56163572A
Authority
JP
Japan
Prior art keywords
address
given
cpu
cancel request
cancel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6625880A
Other languages
Japanese (ja)
Inventor
Shunichi Torii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6625880A priority Critical patent/JPS56163572A/en
Publication of JPS56163572A publication Critical patent/JPS56163572A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To prevent the desorder of the read/write sequence of an instruction for a system in which a main storage device (MS) is shared by plural CPUs incorporating a buffer memory (BS), by adding a means which compares a cancel request address of the BS given from another CPU with the read address of the MS. CONSTITUTION:The figure shows a storage control device exclusive for each CPU. The write address reference requests (cancel request) given from other CPUs are stored in cancel stacks 22-25. When a block transfer becomes necessary from the reference result of a buffer address array BAA to a BS reference request 11a given from a CPU, the reference address of main storage device MS is set to a block transfer address register BTAR30. The contents of stacks 22-25 are compared with the contents of the BTAR through comparators 40-43. Then if an incidence is obtained with an effective cancel request address, the subsequent BS reference requests given from the CPU are suppressed. Thus the BAA reference due to a cancel request and an invalidation of BS are processed in preference.
JP6625880A 1980-05-19 1980-05-19 Data processing system Pending JPS56163572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6625880A JPS56163572A (en) 1980-05-19 1980-05-19 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6625880A JPS56163572A (en) 1980-05-19 1980-05-19 Data processing system

Publications (1)

Publication Number Publication Date
JPS56163572A true JPS56163572A (en) 1981-12-16

Family

ID=13310647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6625880A Pending JPS56163572A (en) 1980-05-19 1980-05-19 Data processing system

Country Status (1)

Country Link
JP (1) JPS56163572A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245861A (en) * 1988-08-06 1990-02-15 Fujitsu Ltd Main storage control system
WO2004107180A1 (en) * 2003-05-30 2004-12-09 Fujitsu Limited Multi-processor system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245861A (en) * 1988-08-06 1990-02-15 Fujitsu Ltd Main storage control system
WO2004107180A1 (en) * 2003-05-30 2004-12-09 Fujitsu Limited Multi-processor system
JPWO2004107180A1 (en) * 2003-05-30 2006-07-20 富士通株式会社 Multiprocessor system
US7320056B2 (en) 2003-05-30 2008-01-15 Fujitsu Limited Multi-processor system

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