JPS61211774A - Vector processor - Google Patents

Abstract

PURPOSE:To make fast the rise of an indirect address instruction and to simplify a control by controlling a reading to the first address buffer register from a vector register in the value of the first address information counter, and controlling an address producing operation by the value of the second address information. CONSTITUTION:During performing an indirect address command, an address read from a vector register VR 6 phases through reading registers 7, 8, 9 to write in the first address buffer register IDQ 15. VR6 has no release signal of a stage A, prohibits the reading when the value of an IOQ counter 17 is above a fixed value, and reopens the reading when the release signal is turned on. Accordingly, in the IOQ 15, the maximum number of data from the VR 6 is constantly contained. The first and the second address buffer registers RQQ counter 18 is above a fixed value, and reopens a transmitting of the request when the value of the RQQ counter 18 is below the fixed value. Thereby, an address information required for producing a request address can be immediately obtained from the IDQ 15 and the rise becomes fast.

Description

[Detailed Description of the Invention] [1 Already Required] An address buffer register is provided between the address generating circuit of the access pipeline and the hector register. As long as there is space, read out the contents (index) of the two-directed atlus from the hector'resku.

This read control.

Since this is performed without receiving information indicating the state of the request address group from the main memory side, the delay in address generation can be reduced.

[Industrial application field]

The present invention relates to a vector processing device.

In particular, the present invention relates to the control of an access pipeline that loads and loads data between a vector register and a main memory.

□ There are two ways to access memory in a vector processing device. One is access with a distance, which is used when processing a large number of data located at a certain distance in main memory at high speed, and the other is high-speed processing of list vectors that collect and execute discrete data in main memory. This is the indirect address access that is taken when

Figure 2 (a+, (bl) shows an overview of the functions of load and store instructions for 3-indirect address access.

In these indirect address instructions, - Little register 1
There is indirect data in main memory 2, \\
Since the register 1 does not represent the element d, through d, but instead contains the index II through I5, it is necessary to read the index data from the vector register 1 before doing the addressing. By adding this index to the start address LA, a request address is generated and supplied to the main memory 2. Thereby, the load (FIG. 2(a)) or store (FIG. 2(b)) of the hector element is performed between the main memory 2 and the hector register 3.

FIG. 3 shows an overview of the functions of load and store instructions with a distance that access data in the main memory at a certain distance (distance d).

These instructions create a request address that sequentially accesses a large number of addresses separated by a distance d in the main memory 2, and loads vector elements with the Hegel register 3 (see Figure 3 (al)). , store (see FIG. 3 (bl)) is performed.

FIG. 4 shows an example of an address mechanism for indirect address load and store instructions in a conventional device, and FIG. 5 shows an address time chart thereof.

In FIG. 4, 4 represents an access pipeline.

5 is a main memory control unit, and 6 is a hector register VR.

9 are read registers RD and RO, respectively.

They are RDR1 and RDR2. Further, IO is an indirect counter, 1) is an address generation circuit, 12 is an address buffer register, 13 is a priority circuit, and 14 is an address pipeline.

To roughly explain the configuration, a plurality of pieces of indirect data stored in the vector register VR are sequentially selected by the access pipeline 4, passed through the read registers RDRO, RDRI, R, and DR2, and then sent to the address generation circuit 1). The input signal is input to one of the adders within the adder. The indirect counter lO is.

Count the number of indirect data for indirect instructions. The other input of the adder is given a logical address LA indicating . ) is supplied to the AT/S conversion circuit. A1ζ
The response conversion circuit converts the logical address into a physical address and converts the logical address into a physical address. Address buffer register 12 of station control unit 5
supply to. The address buffer register 12 is composed of seven register stages and manages a plurality of request addresses in a queue. The priority circuit 13 prioritizes the requests from each access source to the main memory, transfers one selected request to the main memory, and executes the access.

Next, the operation will be explained with reference to FIGS. 4 and 5.

Since the hector resistor VR contains indirect data (index) indicating each vector element, the hector register VR
It is necessary to read the indirect data of . As shown in the time chart of FIG. 5, the indirect counter 10 is set to a predetermined value (here, 12) at the start of the indirect address command, and the indirect address command 1. a The vector register VR is not read under the conditions that the Q-Empty signal is sent from the control unit 5 indicating that there is no request, and that no request remains in the address generation circuit 1).

Furthermore, after reading out the indirect data for 13 stages, the main origin 1. Priority circuit 13 of O control unit 5
Control was performed to change the 13 stages by recognizing whether or not the priority was taken.

However, by doing this, the condition that no request generated by the previous instruction remains in the address generation circuit 1) and main memory control unit 5 is not met unless the previous instruction is completely completed. Until then, the indirect data of the fifth indirect address instruction could not be read from the hex register VR.

[Problem that the invention seeks to solve]

As described above, in the conventional device, the control becomes complicated because the transitions between the 13 stages of stay 1 depend on the rise or delay of the subsequent indirect address command and the priority conditions.

[Means for solving problems]

In order to solve the problems of the conventional device described above, the present invention temporarily holds address information (indirect data) between a 5-hectare register and an address generation circuit when executing 5-hectare address information. A first address buffer register is provided to determine whether or not a previous instruction query 1-71 exists in the 2-address machine side.
< , the address information of the secondary indirect address instruction can be read from the hector register to the first address buffer register only on the condition that there is a certain amount of free space in the address buffer register.

Therefore, in order to manage the empty state of the first address buffer register, an address information counter is provided to count the input and output of address information.

Reading of address information from the vector register to the first address buffer register is controlled by the value of this address information counter.

Furthermore, a second address buffer register is provided on the output side of the address generation circuit to temporarily hold the generated request address, and in order to manage the free state of the register, second address information is provided to manage input and output of the request address. Provide a counter.

The address generation operation of the second address generation circuit is
It is controlled by the value of the address information counter.

[Effect]

According to the present invention, when a certain amount of space becomes available in the first address buffer register, address information is written from the hector register by the first address information counter,
Further, when a certain amount of space becomes available in the second address buffer register, the address generation circuit is activated by the second address information counter. Since the atlus generating circuit can immediately obtain the request address 71 from the reply buffer register, the rise is quick.

〔Example〕

FIG. 1 is a block diagram of an addressing mechanism of a device according to an embodiment of the present invention. In addition, the counter control time chart 1 of FIG. 6 (al and fhl are the first address and software register If)
-, FIG. 7 shows a counter control time chart of the second address buffer register RQQ.

In Figure 1, 4B is an access pipeline.

5 is the above-mentioned 1 quotient control unit, and 6 is the hector register ■R.

9 through 9 are read registers RDRO, respectively.

RDRI, Rr) R2. In addition, lO is an indirect counter, 1) is an amplification circuit, and 13 is a priority circuit. 14 is the address pipeline, 15 is the first
The address buffer register IDC, 16 is the second address buffer register l';! QQ.

17 is an IDQ counter, and 1B is an RQQ counter.

19 is RQQ-FULLO latch, 20 is RQQ-F
UT. , L1 latch, and 21 represents an AND gate. Note that the reference numbers 4 through 14 are used in common with the addressing mechanism of the conventional device shown in FIG.

The address mechanism of this embodiment is provided with a first address buffer register IDQ and a second address buffer register RQQ, and further includes an IDQ counter and R for managing the IDQ.
A feature is that RQQ counters for managing QQ are provided respectively, and the reading of indirect data from the vector register VR is controlled.

Next, the first address buffer register (hereinafter referred to as IDQ) and IDQ counter will be explained.

As can be seen from Figure 1, when an indirect address instruction is executed, the address read from the vector register VR is R.
It is written to TDQ through DRO, RDRI, and RDR2. Therefore, the value of the IDQ counter is incremented by 1 on the condition that an address is written to IDQ or only read from the vector register. Also IDQ power 1
The condition is -1 each time an address is read from the address.

Then, if the hector register VR is shown in Fig. 6 (al. (h
As shown in l. When there is no release signal to the stage of the address mechanism and the value of the IDQ counter is "7" or more, reading is prohibited, and when the release signal of stage A of the address mechanism is turned ON again, reading is restarted.

As a result, IDQ has . Up to 8 pieces of data from the vector register ■[2 can be stored at any time, allowing efficient operation.

Note that No. 6121(a) shows an example in which releases from stage 8 occur continuously. In this figure, the IDQ counter counts up each time an address is written from VR to IDQ.

Releasing begins when the IDQ counter directly reaches "5", and when an address 1 ([I1) is read from IDQ, one is written from VR, and the value of the IDQ counter becomes < 5 for a while. After that, when there is no address to write from the VR, only reading continues from the IDC, and the IDQ counter value is counted down to 0.

Also, Figure 6 (bl) shows an example when the release of stage A is stopped midway.At first, it operates in the same way as in Figure 6 (al), but since the release stops midway, writing to IDQ is not possible. Therefore, the IDQ counter is “7”.
The count amplification is performed up to the point where the writing from the VR is stopped.

Next, address buffer register RQQ and RQQ counter will be explained.

The write conditions for address buffer register RQQ are:
Since a request has been issued from stage R of the address generation circuit section 1), the value of the RQQ counter is +LL, RQ.
The value of the RQQ counter is incremented by 1 since it is read from Q (the priority is taken by the priority circuit 13).

As shown in Figure 7, the condition for inhibiting RQQ writing is that if the value of the RQQ counter becomes "5" or more, the RQQ-FULLO latch is set to 1.
', and at the second timing, set RQQ-FULLI launch to "1", and when both 1 and 1 are "1", an inhibit signal is output from the AND gate and the request is stopped.

In addition, when the value of the RQQ counter becomes less than 4%, request transmission is resumed. As a result, the address buffer register RQQ will not overflow or become empty, and will operate efficiently. do.

By the way, when an instruction with discance is executed in the embodiment configuration of FIG. A discance d is applied to the input.

Added to the logical address of the other input.

The operation of the address generation circuit in this case is the same as when executing the one-direction trace instruction. Controlled by voice.

〔Effect of the invention〕

As explained above, according to the present invention, address buffer registers (TDQ and RQQ) are included in the address generation mechanism.
By providing respective address information counters (IDQ counter and RQQ counter), reading control from vector register VR to address buffer register IDC for 1 indirect address instruction is performed by the value of the IDQ counter. By making it possible to control the address generation for the request address of the address command with distance by the value of the RQQ counter, it is no longer necessary to control the entire stage up to the main memory control unit as in the past.

Even if there is already a previous instruction, reading the data from the vector register in advance will speed up the rise of the two-indirect address instruction.

Control is also easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the addressing mechanism of a device according to an embodiment of the present invention, and FIG. 2 (al) and FIG. 2 (h) are functional overview diagrams of loading and storing indirect address instructions, respectively. FIG. 3 (a) 3 and 3 are functional overview diagrams of load and store instructions with distance, respectively, FIG. 4 is a block diagram of the address mechanism of the conventional device, FIG. ) and Fig. 6 (bl) are time charts of IDQ counter control when the release of A is continuous and when it stops midway, respectively, and Fig. 7 is a time chart of RQQ counter control. In Fig. 1, 6 is a vector register R1, 1) is an address generation circuit, 13 is a priority circuit, 15 is a first address buffer register IDQ, 16 is a second address buffer register RQQ, 17 is an IDQ counter, and 18 is an RQQ counter. There is.

Claims (3)

[Claims] (1) In a vector processing device having one or more vector registers and a main memory, and an access pipeline for transferring data between the vector register and the main memory, an address generation circuit, a vector register and a main memory are provided. A first address buffer register that can store one or more pieces of address information between the address generation circuit and one or more request addresses output from the address generation circuit to the main memory. a second address buffer register for managing the storage status of the first address buffer register; a first address information counter for managing the storage status of the first address buffer register; and second address information for managing the storage status of the address generation circuit and the second address buffer register. When an indirect address load instruction or a store instruction is executed, the reading of address information from the vector register to the first address buffer register is controlled by the value of the first address information counter. done,
A vector processing device characterized in that address generation for a request address is controlled by the value of a second address information counter. (2) In the above item 1, when executing a load instruction or a store instruction with a distance, address generation for the request address is controlled only by the value of the second address information counter. Vector processing unit. (3) In the above item 1, the first address information counter performs an increment count when the first address information counter is written from the vector register to the first address buffer register, and counts when the first address information counter is read from the first address buffer register to the address generation circuit. A vector processing device that performs subtraction counting and controls reading from a vector register such that reading is possible when a first address information counter has not reached a certain value. (4) In paragraphs 1, 2, and 3 above, the second
The address information counter increments each time an access request to the main memory is issued, and decrement each time it is read from the second address buffer register. Alternatively, the vector processing device is characterized in that the condition for reading from the first address buffer register is that the second address information counter does not reach a certain value.