JPH0364902B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] An address buffer register is provided between the address generation circuit of the access pipeline and the vector register, and a certain amount of space is left in the address buffer register when an indirect address instruction is executed. As long as possible, the contents (index) of the indirect address are read from the vector register. Since this read control is performed without receiving information indicating the state of the request address queue from the main memory side, the delay in address generation can be reduced.

[Industrial application field]

The present invention relates to a vector processing device, and particularly to control of an access pipeline that loads and stores data between a vector register and a main memory.

In vector processing devices, there are two ways to access memory. One is access with distance, which is used when processing a large number of data located at a certain distance in main memory at high speed, and the other is list vector, which is used to collect and execute discrete data in main memory. This is indirect address access that is used when processing data at high speed.

FIGS. 2a and 2b show an overview of the functions of load and store instructions for indirect address access.

In these indirect address instructions, vector register 1 contains indirect data, that is, indices I ₁ to I ₅ indicating vector elements d ₁ to d ₅ in main memory 2, so vector register 1 is stored before address generation. It is necessary to read the index data from 1. By adding this index to the start address LA, a request address is generated and supplied to the main memory 2. This allows vector elements to be loaded between main memory 2 and vector register 3 (see Figure 2a).
Alternatively, a store (FIG. 2b) is performed.

FIG. 3 shows an overview of the functions of distanced load and store instructions that access data in the main memory at a certain distance (distance d).

These instructions create a request address that sequentially accesses a large number of addresses spaced apart by a distance d in the main memory 2, and loads vector elements (see Figure 3a) and stores (see Figure 3a) between them and the vector register 3. (see FIG. 3b) is performed.

FIG. 4 shows an example of an address mechanism for indirect address load and store instructions in a conventional device.
The figure shows the address time chart.

In Fig. 4, 4 is an access pipeline;
5 is a main memory control unit, 6 is a vector register VR,
7 to 9 are read registers RDR0, respectively;
They are RDR1 and RDR2. Further, 10 is an indirect counter, 11 is an address generation circuit, 12 is an address buffer register, 13 is a priority circuit, and 14 is an address pipeline.

To roughly explain the configuration, vector register
A plurality of pieces of indirect data stored in VR are sequentially selected by the access pipeline 4 and input to one of the adders in the address generation circuit 11 via read registers RDR0, RDR1, and RDR2. The indirect counter 10 counts the number of indirect data of an indirect command. The other input of the adder is a logical address LA indicating the base address (starting address).
are given, the adder adds these and supplies the result to the address conversion circuit in the address generation circuit 11. The address conversion circuit converts the logical address into a physical address and supplies it to the address buffer register 12 of the main memory control section 5. The address buffer register 12 is composed of a plurality of register stages and manages a plurality of request addresses in a queue. The priority circuit 13 prioritizes requests from each access source to the main memory, transfers one selected request to the main memory, and executes the access.

Next, the operation will be explained with reference to FIGS. 4 and 5. Vector register VR contains indirect data (index) indicating each vector element, so it is necessary to read the indirect data in vector register VR before generating an address. As shown in the time chart of FIG. 5, the indirect counter 10 is set to a predetermined value (12 in this case) at the start of the indirect address instruction in advance, and the indirect counter 10 is set to a predetermined value (here, 12). - Read the vector register VR under the conditions that the Empty signal has been sent and that no request remains in the address generation circuit 11.

Furthermore, after reading out the indirect data for 13 stages, the priority circuit 13 of the main memory control unit 5 recognizes whether or not priority has been taken, and controls the transition of the 13 stages. It was

However, by doing this, unless the previous instruction is completely finished, that is, the address generation circuit 1
The indirect data of the next indirect address instruction cannot be read from the vector register VR unless the condition that no request generated by the previous instruction remains in 1 and the main memory control unit 5 is met. Nakatsuta.

[Problem that the invention seeks to solve]

As described above, the conventional device has problems in that the rise of the subsequent indirect address command is delayed and the control becomes complicated because the states of 13 stages are changed depending on the priority condition.

[Means for solving problems]

In order to solve the problems in the conventional device described above, the present invention provides, when executing an indirect address instruction,
A first address buffer register that temporarily holds address information (indirect data) is provided between the vector register and the address generation circuit, and checks whether the request address of the previous instruction exists in the address mechanism. Regardless of the address buffer register, the address information of the next indirect address instruction can be read from the vector register to the first address buffer register only on the condition that there is a certain amount of free space in this address buffer register.

Therefore, in order to manage the free state of the first address buffer register, an address information counter is provided to count the input and output of address information.
The address information readout from the vector register to the first address buffer register is controlled by the value of this address information counter.

Furthermore, a second address buffer register is placed on the output side of the address generation circuit to temporarily hold the generated request address, and a second address buffer register is installed to manage the input/output of the request address in order to manage the free state of the register. An information counter will be provided.

The address generation operation of the address generation circuit is controlled by the value of the second address information counter.

The configuration of the present invention based on the above provides a vector processing device having a vector register, a main memory, and an access pipeline that transfers data between the vector register and the main memory. a first address buffer register capable of storing a plurality of pieces of address information between them; and a second address buffer register capable of storing a plurality of request addresses outputted from the address generation circuit to the main memory. A first address buffer register that manages the storage status of the register and the first address buffer register.
and a second address information counter that manages the accumulation status of the address generation circuit and the second address buffer register. , the reading of address information from the vector register to the first address buffer register is controlled by the value of the first address information counter, and the address generation for the request address is performed by the second address information. It is characterized in that it is controlled by the value of a counter.

[Effect]

According to the present invention, when a certain amount of space becomes available in the first address buffer register, address information is written from the vector register by the first address information counter, and the address information is written to the second address buffer register. When a certain amount of space becomes available, the address generation circuit is activated by the second address information counter. The address information necessary for the address generation circuit to generate the request address is
Since it can be obtained immediately from the address buffer register, the rise time is faster.

〔Example〕

FIG. 1 is a block diagram of an addressing mechanism of a device according to an embodiment of the present invention. Also, Figures 6a and b are counter control time charts for the first address buffer register IDQ, and Figure 7 is a time chart for the second address buffer register IDQ.
Shows RQQ counter control time chart.

In Figure 1, 4 is an access pipeline;
5 is a main memory control unit, 6 is a vector register VR,
7 to 9 are read registers RDR0, respectively;
They are RDR1 and RDR2. Further, 10 is an indirect counter, 11 is an address generation circuit, 13 is a priority circuit, 14 is an address pipeline, 15 is a first address buffer register IDQ,
16 is the second address buffer register RQQ, 1
7 is IDQ counter, 18 is RQQ counter, 19
is RQQ−FULL0 latch, 20 is RQQ−FULL1
The latch 21 represents an AND gate. Note that the reference numbers 4 through 14 are used in common with the addressing mechanism of the conventional device shown in FIG.

The address mechanism of this embodiment is provided with a first address buffer register IDQ and a second address buffer register RQQ, and further manages the IDQ.
An IDQ counter and an RQQ counter for managing RQQ are provided, and the vector register VR
The feature is that the reading of indirect data from is controlled.

Next, the first address buffer register (hereinafter referred to as IDQ)
) and IDQ counter.

As can be seen from Figure 1, when an indirect address instruction is executed, the address read from vector register VR passes through RDR0, RDR1, and RDR2.
Written to FDQ. Therefore, the value of the IDQ counter is incremented by 1 on the condition that the address has been written to IDQ or read from the vector register, and -1 on the condition that the address has been read from IDQ.

And the vector register VR is
As shown in the figure, when there is no release signal of stage A of the address mechanism and the value of the IDQ counter is "7" or more, reading is prohibited, and when the release signal of stage A of the address mechanism is turned ON again, reading is resumed. Do it like this.

This allows IDQ to include vector register VR
Up to 8 pieces of data can be stored at any time, allowing efficient operation.

Note that FIG. 6a shows an example where releases from stage A occur continuously. In this figure, the IDQ counter increments each time an address is written from VR to IDQ.

When the value of the IDQ counter reaches "5", the release of A starts, and when one address is read from IDQ, one address is written from VR, and the value of IDQ counter remains "5" for a while. After that, when there are no more addresses to write from VR, only reading continues from IDQ, and the IDQ counter value counts down to "0".

Further, FIG. 6b shows an example where the release of stage A is stopped midway. The first was the 6th
It operates in the same way as in Figure A, and since the release stops midway, only writing to IDQ is possible. Therefore, the IDQ counter counts up to “7”, and here
Performs control to stop writing from VR.

Next, address buffer register RQQ and
Let me explain the RQQ counter.

The condition written to the address buffer register RQQ is that a request has been issued from stage R of the address generation circuit section 11, so the value of the RQQ counter is incremented by 1, and the condition is read from RQQ (by the priority circuit 13). Priority has been taken), so the value of the RQQ counter is decremented by 1.

As shown in Figure 7, the RQQ write prohibition condition is that when the RQQ counter value becomes 5 or more, set the RQQ-FULL0 latch to 1,
At the next timing, set RQQ-FULL1 latch to “1”
and if both are “1”, the AND gate outputs a prohibition signal and stops the request.

Furthermore, when the value of the RQQ counter becomes "4" or less, request transmission is resumed. This allows the address buffer register RQQ to operate efficiently without overflowing or becoming empty.

By the way, when executing an instruction with distance in the embodiment configuration shown in FIG. , distance d are applied and added to the logical address of the other input.

The operation of the address generation circuit in this case is controlled by the states of the second address buffer register RQQ and the RQQ counter, similarly to when executing an indirect address instruction.

〔Effect of the invention〕

As explained above, according to the present invention, the address buffer register (IDQ) is added to the address generation unit mechanism.
and RQQ) and address information counters (IDQ counter and RQQ counter), vector registers for indirect address instructions can be used.
Reading control from VR to address buffer register IDQ is performed by the value of the IDQ counter.
Address generation for request address of indirect address instruction and distanced address instruction is
By making it possible to control using the value of the RQQ counter, there is no need to control the entire stage up to the main memory control unit as in the past, so even if there is already a previous instruction, vector By reading the data from the register, the rise of the indirect address command becomes faster and control becomes easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the addressing mechanism of a device according to one embodiment of the present invention, and FIGS. 2a and 2b are functional overview diagrams of loading and storing indirect address instructions, respectively.
3a and 3b are functional overview diagrams of loading and storing instructions with distance, respectively, FIG. 4 is a block diagram of the addressing mechanism of a conventional device, and FIG. 5 is an address time chart of an indirect address instruction. 6th
Figures a and 6b are time charts of IDQ counter control when the release of A is continuous and when it stops midway, respectively, and Figure 7 is a time chart of RQQ counter control. In Figure 1, 6 is a vector register VR;
11 is an address generation circuit, 13 is a priority circuit, and 15 is a first address buffer register.
IDQ, 16 is the second address buffer register
RQQ, 17 represents an IDQ counter, and 18 represents an RQQ counter.

Claims (1)

[Scope of Claims] 1. In a vector processing device having a vector register, a main memory, and an access pipeline that transfers data between the vector register and the main memory, an address generation circuit and a vector register and an address generation circuit are provided. a first address buffer register capable of storing a plurality of pieces of address information between them; and a second address buffer register capable of storing a plurality of request addresses outputted from the address generation circuit to the main memory. , a first address buffer register that manages the storage status of the first address buffer register.
and a second address information counter that manages the accumulation status of the address generation circuit and the second address buffer register. , the reading of address information from the vector register to the first address buffer register is controlled by the value of the first address information counter, and the address generation for the request address is performed by the second address information. A vector processing device characterized in that it is controlled by a value of a counter. 2. In item 1 above, when executing a load instruction or store instruction with distance, address generation for the request address is controlled only by the value of the second address information counter. A vector processing device characterized by: 3 In the above item 1, the first address information counter performs an increment count when the first address buffer register is written from the vector register, and when the first address information counter is read from the first address buffer register to the address generation circuit. A vector processing device that performs subtraction counting and controls reading from a vector register such that reading is possible when a first address information counter has not reached a certain value. 4 In items 1, 2, and 3 above, the second address information counter counts up each time an access request to the main memory is issued, and counts up each time an access request is issued to the second address buffer register. The condition for decrementing and transferring to the second address buffer register and for generating an address or reading from the first address buffer register is that the second address information counter has not reached a certain value. 1. A vector processing device characterized in that the vector processing device performs control such that the vector processing device performs control according to the vector processing method.