JPH06295283A - Computer system - Google Patents

Abstract

PURPOSE:To enable a bus master device on the higher-order bus side to quickly start the next processing at the time of execution of a write cycle continuous from a higher-order bus to a lower-order bus. CONSTITUTION:A bus adapter device 21 arranged between a higher-order bus 17 and a lower-order bus 18 is provided with a higher-order bus slave circuit 22 connected to the higherorder bus 17 and a lower-order bus master circuit 23 connected to the lower-order bus 18, and a FIFO memory 24 and an unpack register 25 are connected between them. When information for write is stored in the FIFO memory 24, the lower-order bus master circuit 23 independently transfers data to the lower-order bus 18 in order. Therefore, the master device on the higher-order bus 17 side is released when information is stored in the FIFO memory 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having two buses having different data bus widths and a bus adapter device for connecting these buses to transfer data, and more particularly, from a high-order bus side to a low-order bus side. The present invention relates to a computer system that enables efficient writing work when writing data to a computer.

[0002]

2. Description of the Related Art In order to process a huge amount of data in a short time, it is strongly desired to improve the processing speed of a computer system. In order to meet such a demand, a so-called data bus width as a data input / output width of a circuit device such as a CPU (central processing unit) and a main memory device which configures a computer system is widened, and the data transfer speed is increased. The speedup is also remarkable. As an example, in a computer system, the CPU has a data width of 64 bits, and the cycle time of data transfer is 15 ns (nanosecond).

As described above, the performance of the computer system is improved, but on the other hand, the compatibility maintenance that the conventional device can be connected to these new computer systems to be utilized is also strong from the viewpoint of effective utilization of hardware design assets. Has been requested. For example, it is necessary to connect a low speed slave device having a data bus width of 8 bits or 16 bits and a cycle time of 200 ns to the high speed computer system as described above.

FIG. 7 shows a conventionally proposed computer system. A CPU 12, a main memory device 13 and an input / output control device 14 are connected to the bus 11. The low-speed slave devices 15 ₁ , 15 ₂ , ... Are the adapter devices 1 for absorbing the difference in the data bus width.
It is connected to the bus 11 via 6 ₁ , 16 ₂ , ....

In such a computer system, the bus adapter devices 16 ₁ , 16 ₂ , ... Are required as many as the low-speed slave devices 15 ₁ , 15 ₂ ,. Therefore,
There is a problem that the amount of hardware that constitutes the system increases. Therefore, there has been proposed a computer system in which a master device and the like are separately connected to a high level bus and a low level bus.

FIG. 8 shows an example of a conventional computer system in which a high level bus and a low level bus are mixed. Here, the high-order bus 17 has a relatively wide data bus width and a relatively high data transfer rate, and the low-order bus 18
Is a bus having a relatively narrow data bus width and a relatively low data transfer rate. In this example, the high bus 17
PU 12, main memory device 13 and input / output control device 1
4 are connected to the low-order bus 18, and several slave devices 15 ₁ , 15 ₂ ... Are connected to the low-order bus 18. A bus adapter device 16 is connected between the high-order bus 17 and the low-order bus 18.

In such a computer system, the bus adapter device 16 needs to absorb the difference in data bus width between the high-order bus 17 and the low-order bus 18. Therefore, a mechanism for disassembling and assembling data is incorporated in the bus adapter device 16. For example, JP-A-61-15176
Japanese Patent Publication No. 9 discloses a mechanism in which the high-order bus 1 has a data bus width of 16 bits and the low-order bus 18 has a data bus width of 8 bits. Further, Japanese Patent Application Laid-Open No. 1-161561 discloses a mechanism in which the ratio of the data transfer sizes of the high order bus 17 and the low order bus 18 is m: 1. Here, the code “m” is a positive integer of 2 or more.

In these conventional techniques, one piece of address information representing an access target is latched in the bus adapter device, and a plurality of bus cycles executed on the low-order bus side (in the later example, m times of bus cycles are executed). The lower addresses are sequentially updated according to the cycle. In the above-mentioned prior art, it is shown that by latching the data in the bus adapter device at the time of the write operation of the CPU, the CPU can be released in advance prior to the update work of the lower address.

[0009]

However, according to such a conventional technique, the bus cycle that can be held in the bus adapter is only one cycle on the high-order bus side. Therefore, even with respect to the preceding release, this can be performed only for one bus cycle of the CPU, and it is not valid until the subsequent write cycle.

Japanese Unexamined Patent Application Publication No. 1-16463 attempts to solve such a problem. In this proposal, an independent data buffer is provided for each of the plurality of channel devices. Therefore, a data buffer is provided for each of the plurality of low-order bus devices, and when a write cycle is executed for different low-order bus devices, a plurality of data buffers are substantially provided in the bus adapter. Addresses for cycles can be stored.

However, even in this proposal, if a continuous write cycle happens to be executed for the same low-order bus device, the corresponding data buffer is one cycle on the high-order bus side. There is no. Therefore, the problem cannot be solved for consecutive write cycles for the same low-level bus device. Furthermore,
In this proposal, it is necessary to prepare an independent data buffer for each channel device. Therefore, there is also a problem that the amount of hardware increases.

Therefore, an object of the present invention is to allow a bus master device on the high-order bus side to quickly shift to the next processing even when executing a continuous write cycle from the high-order bus to the low-order bus. It is to provide a computer system equipped with a device.

Another object of the present invention is to provide a computer system which enables writing to different slave devices on the lower bus side by providing a single buffer in the bus adapter device.

Still another object of the present invention is to obstruct reading of data from the slave device on the low-order bus when writing to different slave devices on the low-order bus side using a single buffer in the bus adapter device. It is to provide a computer system that can be carried out without.

[0015]

According to a first aspect of the invention, (a) a high-order bus for transferring data in a first unit amount and (b) a second unit smaller than the first unit amount. (C) Connect these buses to low-level buses that transfer data in a large amount, and temporarily store the information necessary for writing data from a master device on a high-level bus to a slave device on a low-level bus. The storing means, the acknowledge signal transmitting means for simulatingly transmitting the acknowledge signal indicating that the writing of the data to the slave device is completed to the master device at the time when the above-mentioned information is stored in the storing means, and the storing means. Data recombining means for recombining the stored first unit amount of data into second unit amount of data, and transfer means for transferring the recombined data to the slave device on the lower bus And it is equipped with a bus adapter device to the computer system.

That is, according to the first aspect of the present invention, for example, a master device on the high-order bus is connected to a bus adapter device that connects a high-order bus that transfers data in 32-bit units and a low-order bus that transfers data in 8-bit units. When writing data to the slave device on the low-level bus, prepare a storage means to temporarily store the necessary information for this, store the necessary information for the time being, and wait for the data writing to the low-level bus. Instead, the acknowledge signal sending means sends the acknowledge signal to the corresponding master device in a pseudo manner. As a result, the master device can be released from the constraint without completing the writing of data, and can quickly move to the next process.

According to the second aspect of the present invention, (a) a high-order bus for transferring data in the first unit amount, and (b) data transfer in the second unit amount smaller than the first unit amount. When the master device on the high-level bus is connected to these low-level buses and (c) these buses are connected and data is written to the slave device on the low-level bus, the stored information including the contents of the transfer data, the destination, and the size of the transfer data is stored. A storage means for temporarily storing in the order of accessing the low-order bus, and a pseudo acknowledge signal indicating that the master device has completed writing data to the slave device at the time of storing the stored information in the storage device. Acknowledge signal sending means for sending the data, and a data rearranging means for rearranging the data of the first unit quantity stored in the storage means into the data of the second unit quantity,
A bus adapter device having a transfer means for transferring the recombined data to the destination slave devices on the low-order bus in the order in which they are stored in the storage means, and a bus adapter device having a number of times according to the value indicated by the size information; Prepare for the system.

That is, according to the second aspect of the present invention, for example, a master device on the high-order bus is connected to a bus adapter device that connects a high-order bus that transfers data in 32-bit units and a low-order bus that transfers data in 8-bit units. Storage means such as a FIFO memory for temporarily storing the storage information including the contents of the transfer data, the destination, and the size of the transfer data necessary for writing the data from the low level bus to the slave device on the low level bus. Is prepared, and the stored information is stored in sequence for the time being. Then, at the time of storage of these data without waiting for the writing of data to the low-order bus, the acknowledge signal sending means sends the acknowledge signal to the corresponding master device in a pseudo manner, while the data of the first unit amount stored in the storing means is sent. The data of the second unit is recombined and transferred to the respective slave devices on the low-order bus. This allows
It is possible to realize the data write processing for different slave devices with a single buffer.

According to the second aspect of the invention, the size information of the data transferred from the high order bus to the low order bus is stored in the storage means as a part of the stored information. Using this, the bus adapter device divides the number of times indicated by the size information and transfers, for example, 8-bit unit data to the corresponding slave device.

According to the third aspect of the invention, (a) a high-order bus for transferring data in the first unit amount and (b) data transfer in the second unit amount smaller than the first unit amount. The low-level bus to be performed, and (c) storage means for connecting these buses and temporarily storing information necessary for writing data from the master device on the high-level bus to the slave device on the low-level bus, and this storage. When the above-mentioned information is stored in the means, an acknowledge signal sending means for sending a pseudo acknowledge signal indicating that the writing of the data to the slave device is completed to the master device, and the first signal stored in the storing means. The data recombining means for recombining the unit amount of data into the second unit amount of data, the transferring means for transferring the recombined data to the slave device on the low-order bus, and the information described above in the storing means. Storage presence / absence determining means for determining whether the data is stored or not, and when the master device on the high-order bus reads data from the slave device on the low-order bus, it waits until the storage presence / absence determining means makes a determination of no storage. And a bus adapter device having the means.

That is, according to the third aspect of the present invention, for example, a master device on a high-order bus is connected to a bus adapter device that connects a high-order bus that transfers data in 32-bit units and a low-order bus that transfers data in 8-bit units. When writing data to the slave device on the low-level bus, prepare a storage means to temporarily store the necessary information for this, store the necessary information for the time being, and wait for the data writing to the low-level bus. Instead, the acknowledge signal sending means sends the acknowledge signal to the corresponding master device in a pseudo manner. In addition, a storage presence / absence determining means for determining whether or not the above-mentioned information is stored in the storage means is prepared, and only when the above-mentioned information is not stored, the reading of data from the high-order bus can be performed. By responding to the request, it is possible to prevent the occurrence of a situation in which the information not written in the slave device is read and to read the data without any trouble.

[0022]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows the outline of a computer system according to an embodiment of the present invention. The computer system of this embodiment is composed of a high-order bus 17, a low-order bus 18, and a bus adapter device 21 connecting them. In this embodiment, the high-order bus 17 has a data bus width of 32 bits, and the low-order bus 18 has a data bus width of 8 bits.

The bus adapter device 21 includes a high-order bus 17
A high level bus slave circuit 22 that is connected to the low level bus 18 and functions as a slave device thereof, and a low level bus master circuit 23 that is connected to the low level bus 18 and functions as a master device thereof are arranged. The high-order bus slave circuit 22 is adapted to accept an access from a master device represented by a CPU (not shown) or a DMA (direct memory access) device on the high-order bus 17 side. The low-order bus master circuit 23 is
A write or read cycle is activated a predetermined number of times for various slave devices arranged on the low-order bus 18 side.

The left half of the diagram of the bus adapter device 21 is a circuit portion that functions during a write cycle from the high-order bus 17 to the low-order bus 18, and here, FIFO (first-in first-out) is provided.
A memory 24 and an unpack register 25 are arranged. Also, the right half of the bus adapter device 21 in the figure is a circuit portion that functions during a cycle in which the low-order bus 18 is read from the high-order bus 17, and a data latch circuit 26 and a pack register 27 are arranged here. There is. Hereinafter, the write cycle from the high-order bus 17 to the low-order bus 18 and the read cycle will be described separately.

Write cycle from high order bus to low order bus

The high-level bus slave circuit 22 is connected to the high-level bus 1
7 functioning as a slave device of No. 7 and accepting a write request from the master device on this high-order bus 17. The address information of the received request, the size information of the transfer data, and the transfer data are stored at the end of the FIFO memory 24. When this storage is finished, these are actually
The high level bus slave circuit 22 returns a transfer completion response indicating the completion of the transfer to the high level bus 17 without transferring the data to the high level bus 17. As a result, the corresponding master device such as the above-mentioned CPU on the high-order bus 17 is released from the wait state and the next process can be performed.

Subsequent write processing to the low-order bus 18 is as follows.
The bus adapter device 21 executes asynchronously with the high-order bus 17 side. First, the low-order bus master circuit 23 takes out the address information, the size information of the transfer data, and the transfer data as the oldest storage item stored in the head of the FIFO memory 24. Then, with respect to the address information, if necessary, the upper bits thereof are decoded to generate a slave selection signal for selecting the corresponding slave device of the low-order bus 18. The lower bits are output to the low-order bus 18 side through the low-order bus master circuit 23 as they are.

The transfer data read from the FIFO memory 24 is input to the unpack register 25, decomposed here, and sent to the low-order bus master circuit 23 every 8 bits. The low-order bus master circuit 23 is used in the FIFO memory 2
4 receives the size information of the transfer data, and activates the write cycle on the low-order bus 18 for the number of times indicated in the size information. Then, the 8-bit data discharged from the unpack register 25 is sequentially sent out onto the low-order bus 18 to send out all the transfer data in the FIFO memory 24.

When the write operation for the low-order bus 18 for one entry of the FIFO memory 24 is completed in this way, the write cycle for the next stored information is started by shifting to the next entry. In this way, the low-order bus master circuit 23 operates until all the stored information in the FIFO memory 24 becomes empty.

Read cycle from high order bus to low order bus

Next, the operation when a read request is issued from the high-order bus 17 side to the low-order bus 18 will be described. The high-level bus slave circuit 22 that has received the read request is
The master device on the 7th side is held in a wait state, address information and transfer data size information 41 are sent, and the low-order bus master circuit 23 is activated. Low-level bus master circuit 23
Activates the read cycle for the number of times indicated by the size information of the transfer data while sequentially updating the lower address for the slave device designated by the address information. As a result, data is sequentially read from the corresponding slave device on the low-order bus 18 by 8 bits.

The pack register 27 aligns these read data. Then, these are held in order in the data latch circuit 26. When the data of the required size are all available in the data latch circuit 26,
The high-order bus slave circuit 22 receives the alignment data and sends it to the high-order bus 17, and outputs a transfer completion response signal. The restrained master device receives the data, and the restraint is released by this transfer completion response signal.

Next, the FIFO memory 24 as a circuit characteristic of the computer system of this embodiment and its control will be described in more detail. The lower address update operation on the low-order bus 18 side, the data unpacking operation by the unpack register 25, and the pack register 2
The data packing operation according to No. 7 is not particularly novel as described in, for example, Japanese Patent Application Laid-Open No. 1-161561, and therefore description thereof will be omitted.

FIG. 2 specifically shows a main part of the bus adapter device. The FIFO memory 24 outputs 20-bit address information 51, 2-bit size information 52, and 32-bit transfer data 53 as 1-entry storage information. Of these, the upper 4 bits of the address information 51 are the address decoder 5
5 and is decoded here and slave selection signal 56
Any one of _{0 to} 56 ₁₅ is selected and output to the low-order bus 18. Slave selection signal 5
6 _{0-56 15} is adapted to being connected one by one to the slave device (not shown) connected to the lower bus 18, the selection of the slave corresponding to the output slave select signal 56x is performed.

The remaining 16 bits of the address information 51 are
It is supplied to the address counter 57.
The address counter 57 is supplied with the load signal 59 and the clock signal 61 from the first control circuit 58. Then, the lower bit of the address information 51 is loaded by the load signal 59, and the clock signal 6
At 1, it is incremented by "1".

The size information 52 is supplied to the down counter 63. The first control circuit 58 inputs the load signal 64 and the clock signal 65 to the down counter 63. The size information 52 is loaded into the down counter 63 by the load signal 64 out of these. And
The clock signal 65 decrements the content by "1". As a result, when the count value underflows, the underflow signal 66 is supplied to the first control circuit 58.

The first control circuit 58 outputs the shift signal 69 to the FIFO memory 24 after executing the low order bus cycle a prescribed number of times, and advances the pointer by one. The FIFO memory 24 sends an empty signal 68 to the first control circuit 58 when it has sent all of the stored information.
It is designed to be sent to. Maximum transfer data 53
Up to 2 bits are output in parallel in 8-bit units.

The unpacking register 25 is made enter the shift register 71 ₁ to 71 ₄ of four stages of shifting to the next stage of data 8 bits and configuration connected in series.
These in the shift register 71 ₁ to 71 _4, a first load signal 72 from the control circuit 58 of the clock signal 73 are supplied. Also, the enable signal 74
It is adapted to be supplied to the output buffer 77 to perform the output of the fourth shift register 71 ₄ 8 bits outputted from the transfer data 76 in the final stage.

The first control circuit 58 is used for the low-order bus 18.
Address strobe (AS) signal 78 and read (Read) to activate the bus cycle for
The signal 79 is supplied and an acknowledge signal (ACK) 81 is received from the low-order bus 18.

FIG. 3 shows how the first control circuit is controlled. The first control circuit 58 monitors whether the FIFO memory 24 is empty (step S101). This can be determined by the signal state of the empty signal 68. When the FIFO memory 24 is no longer empty (N), the load signal 59 is sent to the address counter 57 to load the lower 16 bits of the address information 51 into it. Similarly, load signal 6
4, 72 down counter 63 and shift register 71 ₁
Sent to 71 ₄ each is loaded with size information 52 32-bit transfer data 53 (step S10
2).

When the storage information is loaded in this way, the count value set by the down counter 63 is decremented by "1" by the clock signal 65 (step S103). Then, the logical levels of the address strobe (AS) signal 78, the read (Read) signal 79 and the enable (Enable) signal 74 are set to the L (low) level, respectively, and the write cycle is activated (step S104). Then, it waits until the acknowledge (ACK) signal 81 becomes L level (step S105), and when it is confirmed that the transfer data 76 has been written to the low-order bus 18,
Address strobe (AS) signal 78 and enable (E
The enable signal 74 is changed to H (high) level to end the write cycle (step S106).

Thereafter, the count value set by the down counter 63 is further decremented by "1" by the clock signal 65 (step S107). As a result, if the underflow signal 66 is not output (step S108; N), all the transfer data 53 set in the unpack register 25 has not been transferred yet.

Therefore, the address counter 57 is incremented by "1" and the unpack register 2
The shift register 71 in 5 _{1-71 4} clock signal 7
3 and 8 sent to set the next transfer data to the fourth shift register 71 ₄ (step S109). In this example, since the first 8-bit transfer data 76 has been transferred, the contents initially stored in the _third shift register 71 ₃ are stored in the fourth shift register 71 ₄ .

In this state, control again returns to step S104, and the write cycle is activated. And the second 8
The bit transfer data 76 is transferred onto the lower bus 18. Thereafter, in the same manner, the transfer data 76 is sent out to the low-order bus 18 in units of 8 bits up to 32 bits.

If the count value set by the down counter 63 is decremented by "1" and underflow occurs (value is "-1") (step S
108; Y) This means that all the stored information of one entry has been transferred. Therefore, the shift signal 69 is sent to the FIFO memory 24, and the pointer is advanced by one to prepare for the transfer of the next transfer data 53 (return).

By the way, as shown in FIG. 2, the empty signal 68 is also supplied to the high-order bus slave circuit 22. The high-order bus slave circuit 22 does not accept a read request on the high-order bus 17 until the empty signal 68 indicates that the FIFO memory 24 is empty (empty). This is because the data of the address to be read is the FIFO in the bus adapter device 21.
This is to solve the contradiction that occurs when the memory 24 still exists.

FIG. 4 shows how the high-order bus slave circuit is controlled when reading the low-order bus from the high-order bus. The high-order bus slave circuit 22 monitors whether the address strobe (AS) signal of the high-order bus 17 goes low (step S201). When it goes to L level (Y), the low-order bus 18 then reads (Read)
It is checked whether it is an access (step S2)
02). If yes (Y), exit idle and go to F
It waits until the IFO memory 24 becomes empty (step S203). This is because of the reason described above.

When the FIFO memory 24 becomes empty (Y), the address information and transfer data size information 41 are sent to the low-order bus master circuit 23 (step S).
204). As a result, the address decoder in the second control circuit (not shown) in the low-order bus master circuit 23 outputs the corresponding one of the slave selection signals 56 _{0 to} 56 ₁₅ and the read signal 79 goes high. Strobe signal 78 is set to L level.

In this state, the second control circuit operates on the low-level bus 18.
It waits for an acknowledge (ACK) signal 81 to be sent from (step S205). Acknowledge signal 8
When 1 is sent, the read data is low-level bus 18
Since it exists above, it is latched by the data latch circuit 26 via the pack register 27 (step S206). Then, the address strobe signal 78 of the low-order bus 18 is set to H level to terminate the bus cycle for reading (step S207).

Next, the high-order bus slave circuit 22 checks whether or not the number of data read into the data latch circuit 26 matches the size of 8-bit unit shown in the size information (step S208). If they do not match (N), it is necessary to read 8-bit data and add it to the data latch circuit 26. Therefore, returning to step S203, this operation is repeated as many times as necessary.

When the number of data read in step S208 matches the 8-bit size indicated in the size information (Y), the data latched by the data latch circuit 26 is sent to the high-order bus 17 and the high-order bus is also sent. 17
A response indicating that the data has been read out is sent to the master device (step S209), and the control ends (end).

FIG. 5 compares the operations of the high level bus and the low level bus in this embodiment. 7A to 7E show the high-order bus 17 side, of which FIG. 8A shows a clock signal (CLK), and FIG. 7B shows an address strobe signal (AS). The figure (c) shows the address information (Adr), and the figure (d) shows the data signal (Data).
FIG. 6E shows an acknowledge signal (ACK). From time t ₁ , the first address information A ₁ and the first data D ₁ appear on the high-order bus 17, and these are F
Once stored in the IFO memory 24 (FIG. 1), the high order bus slave circuit 22 returns an acknowledge signal to the high order bus 17. From this time t _2, the master device on the side of the high-order bus 17 is released from the constraint and can move to the next process (after A ₂ , D ₂ ).

FIGS. 6F to 7I show the operation on the low-order bus 18 side. FIG. 6F shows the address information (Adr) and FIG. 6G shows the address strobe signal (A).
S) shows the data signal (Data), (h) shows the acknowledge signal (ACK), and (i) shows the acknowledge signal (ACK).

After the high-order bus 17 side stores information such as transfer data in the FIFO memory 24, the first 8-bit address information A _{1 + 0} and data B _{1 + 0} are transferred to the low-order bus 18, and the address strobe signal is sent. Is set to the L level. In this state, when an acknowledge signal indicating the completion of writing is sent from the low-order bus 18, the next second 8-bit address information A _{1 + 1} and data B _{1 + 1} are transferred to the low-order bus 18.
Transferred to. Similarly, the maximum 32-bit transfer data is transferred to the low-order bus 18 in a maximum of four times.

As described above, after the time t ₂ , the address information A _{1 + 0 to} A _{1 + 3} and the data B _{1 + 0 to} B _{1 + 0.}
Regardless of the _{1 + 3} transfer control, the master on the high-order bus 17 can do other work. It should be noted that in this figure, hatching indicates a portion that has no particular meaning in data access, and this also applies to the next FIG. 6.

FIG. 6 compares the operations of the conventional high-order bus and low-order bus for comparison with the computer system of this embodiment. 5A to 5I are respectively shown in FIG.
(A) to (i) of FIG. Conventionally, the first address information A ₁ and the first data D ₁ appear on the high-order bus 17 from the time t ₁ , but they are all written to the corresponding slave device on the low-order bus 18, and the time t ₃ The corresponding master device on the high-order bus 17 is not released from the locked state until the acknowledge signal is returned to.

That is, as shown in FIG. 7F, after the first 8-bit address information A _{1 + 0} and data B _{1 + 0} are transferred to the low-order bus 18 and the address strobe signal is set to the L level. , The next second 8-bit address information A _{1 + 1} and data B _{1 + 1} are transferred to the low-order bus 1 when an acknowledge signal indicating the completion of writing is sent from the low-order bus 1.
8 is transferred.

Similarly, the maximum transfer data of 32 bits is transferred to the low-order bus 18 in a maximum of 4 times.
When all the data transfer on the low-order bus 18 is completed, the acknowledge signal shown in FIG.
The constraint will be released when it is sent to the above and the corresponding master device recognizes it. Therefore, the restraint time T ₂ is usually much longer than the restraint time T ₁ shown in FIG.

In the above description, the case where the master device on the high-order bus 17 transfers write data for one time to one slave device has been described. However, the same master device writes to a plurality of different slave devices. In some cases, data may be continuously transferred in order. FIG. 5 shows such a state. From time t ₄ , the second address information A ₂ and the second data D ₂ appear on the high-order bus 17, and similarly, this signal is generated by the acknowledge signal from the bus adapter device 21. The control for the second writing is ended. And time t
_{From 5} to 3, the third address information A ₃ and the third data D ₃ will appear on the high-order bus 17. The same applies hereinafter.

It is natural that the FIFO memory 24 for sequentially storing the address information A ₁ etc. enables the continuous control by the same master device, whereby the same master device can operate in a shorter time. It is understood that a plurality of data can be transferred to the lower bus 18 side. Of course, in the FIFO memory 24, not only the same master device but also different master devices can store the information for each write access.

In the embodiment described above, the high-order bus slave circuit 22 and the low-order bus master circuit 23, which are commonly used for writing and reading, are arranged in the bus adapter device 21. However, these are circuit configurations separated for each use. May be. Further, the memory for storing the address information for writing does not have to be limited to the FIFO memory, and the range of the number of stages is not particularly limited as long as it is a plurality of stages.

Further, in the embodiment, the data previously input to the FIFO memory is read out first and the slave device on the low-order bus is written. However, the transfer data for the same slave device is collectively extracted. Alternatively, these may be transferred in order of time. This allows the low level bus to be used more efficiently.

In the embodiment, when the high-order bus requests the low-order bus to read data, the data is read after waiting for all the data in the FIFO memory to be transferred. It is determined whether or not the transfer data destined for is stored in the storage means such as the FIFO memory, and if not stored, the data is read even if the storage information destined for another slave device is stored in the storage means. May be executed.

[0065]

As described above, according to the first aspect of the present invention, data is written from the master device on the high order bus to the slave device on the low order bus in the bus adapter device connecting the high order bus and the low order bus. At this time, a storage means for temporarily storing the necessary information is prepared, and at the time when the necessary information is stored in the storage means, the acknowledge signal transmitting means does not wait for the writing of data to the low-order bus, Is sent to the corresponding master device in a pseudo manner. For this reason, the master device can release the constraint for writing data and perform other work without waiting for the arbitration time for the low-order bus, so that efficient operation of the computer system can be achieved. .

According to the second aspect of the invention, when data is written from the master device on the high order bus to the slave device on the low order bus in the bus adapter device connecting the high order bus and the low order bus, the transfer data A storage means such as a FIFO memory for temporarily storing the storage information including the content, the destination, and the size of the transfer data in the order of accessing the low-order bus was prepared. Therefore, not only can data be efficiently transferred to a plurality of slave devices,
Store the stored information in the order in which it is acknowledged to the lower bus,
Since the data is transferred in this order, the data can be processed in time series, and the accuracy of the processing can be ensured.

Further, according to the second aspect of the present invention, since the size information is stored in the storage means as a part of the storage information, the bus adapter device side stores the first unit amount of data on the high level bus side in the second unit. It is not necessary to unconditionally transfer the entire amount in the form of being divided into unit amounts, and it is sufficient to transfer only the number of times according to the size information. Therefore, no waste occurs in the data transfer to the lower bus.

According to the third aspect of the present invention, the information necessary for writing the data from the master device on the high order bus to the slave device on the low order bus in the bus adapter device connecting the high order bus and the low order bus. A storage means for temporarily storing is stored, and not only the necessary information is stored in the storage means, but also a determination means for determining whether or not the storage means is emptied, Since I decided to allow reading data from the high-order bus to the low-order bus,
It is possible to prevent a situation in which information before being updated is read by the slave device on the low-order bus side.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an outline of a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram specifically showing a main part of a bus adapter device of the present embodiment.

FIG. 3 is a flow chart showing a control state of a first control circuit in the present embodiment.

FIG. 4 is a flow chart showing how the high-order bus slave circuit is controlled when reading the low-order bus from the high-order bus in the present embodiment.

FIG. 5 is a timing diagram comparing operations of the high-order bus and the low-order bus in the present embodiment.

FIG. 6 is a timing diagram comparing operations of a conventional high-order bus and low-order bus for comparison with the computer system of the present embodiment.

FIG. 7 is a system configuration diagram showing a conventionally proposed computer system including one bus.

FIG. 8 is a system configuration diagram of a conventional computer system in which a high-order bus and a low-order bus are mixed.

[Explanation of symbols]

12 ... CPU, 13 ... main memory device, 14 ... input-output controller, 15 _1, 15 ₂ ... slave device, 17 ... high bus, 18 ... lower bus, 21 ... bus adapter device, 22 ...
High-order bus slave circuit, 23 ... Low-order bus master circuit, 2
4 ... FIFO memory, 25 ... unpack register, 2
6 ... Data latch circuit, 27 ... Pack register, 5
5 ... Address Decoder, 57 ... Address Counter, 58
... first control circuit, 63 ... down counter, 71 _{1 to} 7
1 ₄ ... shift register

Claims (3)

[Claims] 1. A high level bus that transfers data in a first unit amount, a low level bus that transfers data in a second unit amount that is smaller than the first unit amount, and these buses are connected. A storage means for temporarily storing information necessary for writing data from a master device on the high-order bus to a slave device on the low-order bus, and to the master device when the information is stored in the storage means. Acknowledge signal transmission means for artificially transmitting an acknowledge signal indicating that the writing of data to the slave device is completed, and the first unit amount of data stored in the storage means is converted into the second unit amount of data. Computation, comprising: a data adapter for recombining data; and a bus adapter device having a transfer device for transferring the recombined data to the slave device on the low-order bus. System. 2. A high level bus that transfers data in a first unit amount, a low level bus that transfers data in a second unit amount that is smaller than the first unit amount, and these buses are connected. A storage means for temporarily storing, when writing data from the master device on the high-level bus to the slave device on the low-level bus, stored information including the content and destination of the transfer data and the size of the transfer data in the order of accessing the low-level bus. And an acknowledge signal sending means for sending a pseudo acknowledgment signal indicating that the master device has finished writing data to the slave device when the storage information is stored in the storing device, and the storing device. Data rearrangement means for recomposing the stored first unit amount of data into second unit amount of data, and the recombined data in the order of being stored in the storage means. In the computer system, characterized by comprising a bus adapter device provided with a transfer means for transferring by the number of times corresponding to the value indicated by the size information to the slave device of each destination on low bus. 3. A high level bus that transfers data in a first unit amount, a low level bus that transfers data in a second unit amount that is smaller than the first unit amount, and these buses are connected. Storing means for temporarily storing information necessary for writing data from the master device on the high-order bus to the slave device on the low-order bus, and to the master device when the information is stored in the storing means. Acknowledge signal transmission means for artificially transmitting an acknowledge signal indicating that the writing of data to the slave device is completed, and the first unit amount of data stored in the storage means is converted into the second unit amount of data. Data recombining means for recombining, transfer means for transferring recombined data to the slave device on the low-order bus, and determining whether or not the information is stored in the storing means A bus adapter device having a storage presence / absence determining means and a read standby means for making the storage presence / absence determining means wait until the master device on the high level bus reads data from the slave device on the low level bus A computer system comprising: