JPS63147245A - Memory access system - Google Patents

Abstract

PURPOSE:To improve the high-speed working performance of a processor consisting of a CPU and a memory by comparing an address obtained in a memory access with the contents of a boundary register to activate exclusively two different signal lines and at the same time outputting continuous addresses at the time of memory access. CONSTITUTION:The contents of storage are compared with each other between an address register 5 and a boundary register 4. Then the output of a comparator 6 is set at L if the address value is smaller than the boundary value. Then the output of an AND gate 7-4 and an OR gate 7-10 to which the inverted data are applied are set at H and a signal line 7-2 is active in place of a signal line 7-1. Thus a high-speed ROM storing the data having high using frequencies is selected. Then the ROM receives an access with two continuous address produced by a +1 circuit 8-1 and a selecting circuit 8-2. As a result, the access speed is increased for a processor consisting of a CPU and a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method in a data processing device comprising a central processing unit and a memory.

[Prior Art and Problems to be Solved] Conventionally, cache memory has been used in data processing devices to shorten memory access time, which determines performance.

However, in the conventional cache memory method, in addition to the access time of the cache memory itself, the operation time of a large amount of cache directory and many comparators that compare the cache directory with the memory access address is required, and the access at the time of hit/miss This results in an increase in time. Furthermore, this method also has the disadvantage of requiring a large amount of hardware.

[Means for Solving the Problems] The present invention solves the above-mentioned conventional problems. In a memory access method of a data processing device consisting of a central processing unit and a memory, the central processing unit uses a plurality of signal lines and addresses indicating the type of access. line, data line, boundary register, address register, a comparator that compares the address at the time of memory access with the boundary register, means for exclusively activating two different signal lines at the time of memory access based on the comparison result, and furthermore at the time of instruction access. It has a configuration having means for outputting consecutive memory addresses.

[Example] Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a bus side interface circuit of a central processing unit using an embodiment of the present invention.

In the figure, 1-1 is a signal line indicating an instruction fetch request;
1-2 is a signal line indicating memory write, 7-1 is a signal line indicating low-speed memory access, 7-2 is a signal line indicating high-speed memory access, 9-5 is a signal line for manually inputting a memory wait signal, 2 3 is a signal line indicating an address, and 3 is a transmission/reception line for read data/write data.

Further, 5 is an address register, and 4 is a high-speed/low-speed memory boundary register, indicating that the address indicated by this register or higher is a low-speed memory.

6 is a comparator, 8-1 is a +1 circuit, 8-2 is a selector, 8-4 is a set-reset flip-flop for instruction fetch requests, 8-5 is a set-reset flip-flop for data fetch requests, 8- 6 is a set/reset flip-flop for data writing.

Furthermore, 8-4a, 8-5a, and 8-6a are request request terminals, respectively. 9-3 is a D-type flip-flop which autonomously returns a memory ready signal and releases a request during high-speed memory access. A data register 9-1 holds read/write data. 7-3~7
-8 is an AND gate, and 7-9 to 7-10 are OR gates, which respectively create signals for low-speed memory access and high-speed memory access.

FIG. 2 shows a memory system connected to the central processing unit of this embodiment, in which 10-1 is a high-speed static memory chip, 10-2 is a path buffer for data direction switching, and 10-3 is a dynamic RAM. This is a memory system that has a continuous two-word access function (so-called nibble mode).

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. At the time of instruction fetch access, an access address is first set in address register 5 by microcode or advance control hardware. Then, the address for making an access request to the request request terminal 8-4a is compared by the comparator 6. If the memory is a low-speed memory, the comparator output becomes 1, the AND gate 7-3 becomes 1, and the
The R gate 7-9 also becomes 1. As a result, signal line 1-
1.7-1 becomes 1, and since it is not a write request, the signal line 1-2 becomes 1. As a result, the memory system 10-3 in FIG. 2 operates to take in and latch the address. Memory system 10-3 performs nibble mode access and returns two words of data. At the time of return, the signal line 9-5 is set to 1 from the memory system 10-3, so the set-reset flip-flop 8-4 is reset and the access is completed. The data register 9-1 is a double buffer and takes in data for two words. Although the memory system 10-3 can be designed to have any speed by delaying the timing of returning the signal on the signal line 9-5 on the memory side, it is difficult to achieve high speed.

Note that the address changes by +1 circuit 8-1, selector 8-2, and D type flip-flop 8-3 in one access, but the memory system 10-3 ignores the address that has been increased by +1. Continuous addresses are accessed using the nibble mode access function of 10-3.

Next, a case where the comparator output is 0 in a similar access will be described. In this case, the signal line 7-2 is set to 1 by the AND gate 7-4 and the OR gate 7-10, indicating high-speed memory access, and the static RAM 10-1 is chip-selected. At the first clock after access, the address is switched by +1 by the D type flip-flop 8-3, and at the same time, the first word data is latched into the double buffer 9-1. Further, the data at the address incremented by 1 at the first clock is latched. In this way, instructions for two words can be read in two clocks. Since the processor requires one clock to prepare the address, it can read two words in three clocks.

Furthermore, since no special circuit is required on the high-speed memory side, access can be made by taking advantage of the speed of the static RAM 10-1.

Next, when reading data and writing data, only one word is accessed without changing the address.

In any case, since only a comparison is required to determine whether the memory is high speed memory or low speed memory, the delay is small and the high speed memory can be accessed without loss.

Furthermore, high performance can be achieved by storing frequently appearing program data in the high-speed memory.

[Effects of the Invention] As explained above, the present invention provides a memory access system for a data processing device comprising a central processing unit and a memory.
The central processing unit has multiple signal lines that indicate the type of access, an address line, a data line, a boundary register, an address register, a comparator that compares the address during memory access with the boundary register, and two different signal lines depending on the comparison results. By having a means to activate exclusively during memory access and a means to output continuous memory addresses during instruction access, the memory can be divided into high speed and low speed and high speed memory access can be performed without loss, improving the system as a whole. Performance can be improved. This is effective in systems with embedded software in which program behavior is fixed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus interface portion of a processor employing a memory access method according to an embodiment of the present invention, and FIG. 2 is a block diagram of a memory system connected to the processor employing the present invention. 1-1.1-2.2゜7-1.7-2.9-5: Signal line 4: Boundary register 5 Near address register 6: Comparator 8-1: +1 circuit 8-2: Selector 8-3 .9-3: D type flip-flop 8-4.8
-5.8-6 Two-set reset flip-flop block 9-1: Data registers 7-3 to 7-8: AND gates 7-9 to 7-10: OR gate 10-1: High-speed static memory chip 10-2 :
Bus buffer 10-3: Memory system

Claims (1)

[Claims] In a memory access method for a data processing device consisting of a central processing unit and memory, the central processing unit uses multiple signal lines that indicate the type of access, address lines, data lines, boundary registers, address registers, and boundary registers that indicate addresses during memory access. A memory access system characterized by comprising: a comparator for comparing the data, a means for exclusively activating two different signal lines at the time of memory access according to the comparison result, and further a means for outputting continuous memory addresses at the time of instruction access.