JPS61114351A - Memory controller - Google Patents

Abstract

PURPOSE:To decrease the number of data lines and also to attain the use of a memory with high efficiency by making use of the idle time between the input/output of the data and that of the next data for input/output of data on another dynamic RAM. CONSTITUTION:A memory controller 1 controls a memory block consisting of plural pieces of dynamic RAMs. Both address and data lines (d) and (a) are provided in common with all dynamic RAMs contained in the memory block. While control lines (b) and (c) are set independently of each other for each dynamic RAM. Then each dynamic RAM receives the time-division input/ output control by the control signals supplied via both lines (b) and (c) and via both common lines (d) and (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory control device for controlling write timing or read timing of a memory to appropriate timing, and in particular, to a memory control device configured with a plurality of dynamic RAMs. The present invention relates to a memory control device suitable for use in image memories and the like.

[Background of the invention]

Generally, image memory is one screen worth (one frame)
This is a memory for storing digital image information corresponding to 0, and is used for digital image processing. As mentioned above, since the image memory can only store image information for one screen, the stored image information is successively rewritten with new information. ) 1. Stop writing to the image memory and start reading at a certain moment,
A still image can also be obtained by repeatedly displaying the read information on the screen.

By the way, when digital image information is D/A converted to display an image on a screen, it is necessary to shorten the period of the digital image information (data sampling period) in order to obtain a higher definition image. Furthermore, in order to accommodate such digital image information, the capacity of the image memory must be increased and high-speed access is required.

In general, image memory is a highly integrated dynamic RA.
M is often used, however, because the cycle time in the random read/write mode of dynamic RAM is long, high-speed access is impossible, and the operation cannot follow the input/output digital image information. . That is, for example, an image signal (image information) is sampled at a sampling period of approximately 70 ns (the sampling frequency is four times the subcarrier frequency of the television NTSC system), and converted by an 8-bit A/D converter. When a digital signal (digital image information) is obtained using a TV screen, the capacity of the image memory (hereinafter sometimes referred to as frame memory) to store one frame of the television screen is approximately 3.8 Mbits. It is. Then, the cycle time of that frame memory is 2.
60ns 256 words x 1 bit dynamic R
If AM is used, as described above, the cycle time of the dynamic RAM will be longer than the sampling period, making it impossible to follow the operation.

Therefore, in the past, a plurality of dynamic RAMs were used to increase the apparent operating speed through serial-to-parallel conversion. In other words, taking the case of writing as an example, data that is serially sent one after another is temporarily stored in a bumper register, and then written to multiple dynamic RAMs arranged in parallel, predetermined bits at a time. was. However, this method has the problem that data lines are required for the number of dynamic RAMs, and since each dynamic RAM is highly integrated, the number of dynamic RAMs can be increased by serial/parallel conversion. There was also the problem that an increase in the memory capacity of the entire system would result in a surplus of memory.

For example, if serial/parallel conversion is performed for 4 bits at a time, 4 dynamic RAMs are required in parallel, and if the data is input at 8 pins, the entire frame memory will require 32 dynamic RAMs.
The total capacity will be 8M bits. However, as mentioned above, the actual required capacity is only 3.8 Mbits, which results in a surplus of about 4 Mbits, which is extremely uneconomical.

Therefore, in order to efficiently utilize memory capacity, dynamic RAM having a high-speed mode has conventionally been used. That is, dynamic R with fast mode
In AM, for example, if you select nibble mode, which is a high-speed mode, data can be input/output continuously for 4 bits, and the cycle time for 4 bits is 270n.
It becomes s.

Therefore, when applied to the example described above, the number of dynamic RAMs used is 16, and it can be seen that there is almost no surplus memory.

However, this does not essentially solve the problem of reducing the number of data lines, which is another problem.

Incidentally, examples of devices related to such reduction of data lines and the like include those described in Japanese Patent Application Laid-Open No. 57-20979. The method described in this publication uses the address line and the data line in common, that is, the address signal and the data signal are time-divided and supplied on one line.

[Purpose of the invention]

The purpose of the present invention is to solve the problems of the prior art described above,
To provide a memory control device capable of reducing the number of data lines between each memory, reducing or omitting serial/parallel conversion, and efficiently utilizing memory capacity. It is in.

[Summary of the invention]

The data line connected to the dynamic RAM is idle and is not used after data is input/output until the next data is input/output. The present invention focuses on this and uses the idle time of such data lines for inputting/outputting data of other dynamic RAMs, thereby allowing data lines of multiple dynamic RAMs to be connected while maintaining high speed. I decided to share it.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In Figure 1, ■ and ■ are dynamic RAs with a 256 word x 1 bit configuration that operate in nibble mode.
M,1 is a memory control device according to the present invention. The memory control device 1 includes a RAS-CAS generation circuit 2, an address generation circuit 3, a switch 4, an input terminal 5, and an output terminal 6.
and a clock input terminal 7, respectively. Here, the RAS/CAS generation circuit 2 is a circuit that generates two types of control signals, RAS signal and CAS signal, respectively.
The RAS signal and CAS signal are connected to the control line ◎ (RAS
It consists of two lines: a line and a CAS line. ) to the dynamic RAM ■, and control line 0 (RAS line and CAS
It consists of two lines. ) are respectively input to the dynamic RAM (2).

Further, the address generation circuit 3 operates as a counter,
Appropriate addresses are given to the dynamic RAMs (2) and (2), respectively, via the address line (2) (commonly connected to the two dynamic RAMs (2)). Furthermore, R.A.S.
-RAS signal output from CAS generation circuit 2, CA
The timings of the S signal and the address signal output from the address generation circuit 3 are synchronized by the clock input from the clock input terminal 7. The switch 6 is a switch for switching input and output, and when writing, it is closed to the a side to directly connect the input terminal 5 and the data line ■, and when reading, it is closed to the b side to connect the output terminal 6 and the data line ■.
are directly connected. In addition, the data line ■ is a dynamic RA
Commonly connected to M■ and ■. In addition, as digital data (digital signal) input from the input terminal, a video signal is sampled at 4XfiC=14.3MH, (AsC is color subcarrier frequency) and sent to an 8-bit A/D converter (not shown). However, in order to simplify the diagram, only one bit of output from the A/D converter is shown in FIG. 1.

Now, before explaining the operation of this embodiment, the operation of a general dynamic RAM in nibble mode will be explained.

FIG. 2 is a timing chart of write cycles and read cycles when the dynamic RAM operates in nibble mode. In FIG. 2, the shaded area is indeterminate.

As shown in FIG. 2, in the dynamic RAM, a row address is set at the fall of the RAS signal, a column address is set at the fall of the CAS signal, and the address is determined by the above steps. Then, in the case of a write cycle, the data (2) that is coming to the data line at that time is written to the determined address. What has been described so far is the normal operation of the dynamic RAM. Furthermore, in subsequent operations in nibble mode, toggling the CAS signal causes data to be written on each falling edge of the CAS signal.
That is, three pieces of data (2), (2) and (2) are written consecutively. In this way, in the nibble mode, 4-bit data can be written or read during the cycle time tie.

By the way, as can be seen from Figure 2, of the cycle time txc in nibble mode, the dynamic RAM
The time during which the data line is actually used is only during tND, including the write cycle and read cycle. Therefore, in the present invention, as described above, attention has been paid to this point, and the idle time of the data line is used effectively.

Now, the operation of this embodiment will be explained with reference to FIGS. 1 and 3.

FIG. 3 is a timing chart of main signals in FIG. 1. In FIG. 3, it is assumed that ■ and ■ correspond to dynamic RAM ■ and dynamic RAM ■ shown in FIG. 1, respectively.

During a write operation, first, the switch 4 shown in FIG. 1 is closed to the a side. As mentioned above, one of the video signals digitized by the A/D converter (not shown) is
Bit data is sent to the memory control device 1 from the input terminal 5.
The signal is input into the data line 4 and transmitted to the data line 3 via the switch 4. Since the sampling frequency is 14.3 MH as described above, data is input from the input terminal 5 every 70 ns.

Therefore, the RA input from the 11th CAS generation circuit 2 to the dynamic RAM via the control line @
The address of the dynamic RAM ■ is determined by the S■ signal, the CAS■ signal, and the address signal input from the address generation circuit 3 via the address line O, and data is written. That is, as shown in Figure 3, RAS
■Signal and CAS■signal in synchronization with each other,
By inputting the address for dynamic RAM 0 (row address and column address), the address of dynamic RAM ■ is determined, and then 4 consecutive
Bit data, ie, to. ■The data between is written.

On the other hand, while 4-bit data is being continuously written to the dynamic RAM, preparations for writing are made to the dynamic RAM (2). That is, the RAS@ input from the RAS-CAS generation circuit 2 shown in FIG. 1 to the dynamic RAM ■ via the control line O
An address for writing is prepared in the dynamic RAM (2) by the CAS (2) signal and the address signal inputted from the address generation circuit 3 via the address line (3). And, as shown in Figure 3,
Immediately after writing to the dynamic RAM is completed (time 1-1.), writing to the dynamic RAM begins, and 4 bits of data are continuously written, that is,
Data between tND■ is written to the dynamic RAM■.

Also, at this time, similar to the previous cycle, write preparations are made to the dynamic RAM, and the dynamic RAM
When the writing of 4-bit data to ■ is completed,
Make sure that writing to the dynamic RAM begins immediately (.

Then, similar operations are repeated thereafter.

On the other hand, during a read operation, each dynamic RAM is changed from the write mode to the read mode, and the switch 4 is closed to the b side. Then, data is read out from each dynamic RAM and outputted from the output terminal 6 in substantially the same manner as the write operation. Furthermore, at this time,
The data read from each dynamic RAM is the image data written immediately before switching to the read mode. The data output from the output terminal 6 may be converted into an analog signal by a D/A converter (not shown).

According to this embodiment, by using the nibble mode, which is a high-speed mode, serial-to-parallel conversion, which is a means to increase the apparent speed, can be reduced or omitted, and Capacity can be used efficiently. Further, according to this embodiment, by applying the RAS signal, the CAS signal, and the address signal to the two dynamic RAMs at appropriate timings, data input/output is time-shared in the two dynamic RAMs, and the data There is no problem even if the line is shared.

Next, other embodiments of the present invention will be described.

FIG. 4 is a block diagram showing another embodiment of the present invention.

In FIG. 4, parts with the same symbols as in FIG. 1 have the same functions. In addition, O20 is a dynamic RAM that operates in nibble mode, 8 is a switch, and 9 is a dynamic RAM that operates in nibble mode.
．． 10 are latch circuits, respectively.

In the configuration of this embodiment, the sampling frequency is too high, and the first
The configuration shown in the figure is a configuration used when the memory speed cannot keep up. That is, in this embodiment, in order to perform high-speed operation, a switch 8. is newly installed in the memory control device 1. Launch circuits 9 and 10 are added, and the operation contents of the address generation circuit 3 are also different. In this embodiment as well, the digital signal input from the input terminal is a video signal of 8
The input is converted by a focus A/D converter (not shown), but in FIG. 4, as in the case of FIG.
Only one bit of output from the D converter is shown.

Now, the operation of this embodiment will be briefly explained.

During write operation, switch 4 is closed to side a,
Data input from the input terminal 5 is input to the switch 8 via the switch 4. The data input to the switch 8 is alternately distributed one bit at a time to the latch circuit 9 and the latch circuit 10 by the switching operation of the switch 8. It should be noted that these latch circuits 9 and 10 are for holding the input data from the time the data is input until the next data is input. Therefore, data is input to the input terminal 5 one bit at a time, Dr and Dz.

Ds, D4. ...... is input, the switch 8 first inputs Dl to the latch circuit 9, then the switch 8 switches, and the latch circuit 10 inputs Dl.
8 is input. Then, the switch 8 is switched again and the latch circuit 9 is inputted.

Then, the launch circuit 9 outputs the held Dl to the data line (2). When the switch 8 is switched again and D4 is input to the latch circuit IO, the launch circuit 10 outputs the held Dt to the data line [phase]. The same operation is repeated thereafter.

The data input to the data line ■ is written to and 0 of the dynamic RAM, and the data input to the data line [phase] is written to the dynamic RAM @ and @, respectively, in the same manner as in the above-described embodiment. .

Note that the read operation can be easily understood from the write operation described above, so a description thereof will be omitted.

According to this embodiment, the speed of data outputted to one set of dynamic RAM (■ and ■ or O and @) by the switch 8 and the latch circuits 9 and 10 is equal to or equal to the speed of data input to the input terminal 5. , the speed of data output from the output terminal 6 is half, and apparently high-speed operation is possible.

Now, here, the memory control device 1 and each dynamic RAM
Let's compare the number of connections with the conventional device.

In conventional memory control devices, switch 8. Lattern circuit 9
．． 10 is provided with a bumper register as described above, and during the writing preparation period and write operation of the dynamic RAM, the data that is serially input from the input terminal is stored in the bumper register, and the data is stored in the bumper register. At the same time, 4
4 bits were written to each dynamic RAM. Therefore, the output 1 of the 8-bit A/D converter
The number of data lines between the dynamic RAM and the memory control device is four for each bit. Furthermore, if we consider 8 bits of output from the A/D converter, the number of data lines is 32. Further, since the address line and control line are common to all dynamic RAMs, the number of them is one each.

On the other hand, in this embodiment, as shown in FIG.
The number of data lines between the dynamic RAM and the memory control device 1 for one bit of output from the /D converter is as follows:
Therefore, if we consider the 8-bit output of the A/D converter, the number of data lines is 2 (■ and @).
There will be 8-16 pieces.

Also, as shown in Figure 4, the number of address lines is one (■), and the number of control lines is two (◎ and O), but since these are common to other dynamic RAMs, A/ The number does not increase even for the 8-bit output of the D converter.

In this way, according to this embodiment, there is only one control line (
Here, one control line means two lines, the ■ child line and the CAS line. ), the number of data lines can be halved, making it easier to implement high-density packaging and integrate memory control devices into integrated circuits.

In the embodiments shown in FIGS. 1 and 4, the data line is used in common for writing and reading, but the data line for writing and the data line for reading are It is also possible to make them independent, and use a read-modify-write cycle to read data from one frame before while writing new data to the same address. Also, in both embodiments,
Although two memories are described as one set, the same operation can be performed sequentially with a larger number of memories as one set. In other words, when memory A finishes inputting or outputting data, memory B simultaneously inputs or outputs data. inputs or outputs data,
Furthermore, it is also included in the present invention that when the memory B finishes inputting or outputting data, the memory C inputs or outputs data at the same time.

〔Effect of the invention〕

According to the present invention, for example, as in the embodiment shown in FIG.
The number of data lines can be halved and high speeds can be maintained.
The number of wires between each memory and the memory control device can be reduced. Furthermore, this facilitates high-density packaging, facilitates integration of the memory control device into an integrated circuit, and reduces costs. Furthermore, it is possible to reduce the number of serial-to-parallel conversions of the dynamic RAM, and to make efficient use of the dynamic RAM.

To give a specific example, as mentioned above, the cycle time is 260
Dynamic R with word x 1 bit configuration in 256 ns
When constructing a frame memory with a sampling time of 70 ns in AM, a capacity of about 3.8 Mbits per frame is required for 8-bit input and NTSC television. Furthermore, since the cycle time is longer than the sampling time, 4-bit serial/parallel conversion is required, and 32 dynamic RAMs are required, resulting in a surplus memory of about 4 Mbits. Further, there are 64 data lines with the input and output of the dynamic RAM being made independent. Therefore, if we decide to use nibble mode, which is a high-speed mode of the dynamic RAM mentioned above, and assume that the 4-bit cycle time is 270 ns, the serial
Parallel conversion can be omitted and dynamic RA
The number of M is only 16, and the surplus memory can be reduced.

Furthermore, there are 16 data lines with the input and output of the dynamic RAM being made independent.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of a write cycle and a read cycle when dynamic RAM operates in nibble mode,
FIG. 3 is a timing chart of main signals in FIG. 1, and FIG. 4 is a block diagram showing another embodiment of the present invention. Description of symbols 1...Memory control device, 2...■τ and τ generation circuit, 3...Address generation circuit, 4...Switch,
5... Input terminal, 6... Output terminal, 7... Clock input terminal, 8... Switch, 9.10... Launch circuit, ■. ■, 0.0...Dynamic RAM, ■, ■...Data line, ■, O...Control line, O...Address line Agent Patent Attorney Akio Namiki Figure 1

Claims (1)

[Claims] 1) In a memory control device for controlling one or more memory blocks constituted by a plurality of memories, address lines and data are connected to all memories included in one memory block. Connect the lines in common, and connect the control lines to each memory.
A memory characterized in that the input/output of each memory included in one memory block is time-divisionally controlled using a common address line and data line by a control signal supplied via the control line. Control device. 2) In the memory control device according to claim 1, the memory block is used as a frame memory for image processing, each memory constituting the memory block is composed of a nibble mode dynamic RAM, and each memory @CA of the control signals input to
A memory control device characterized in that input/output control is performed on each memory regarding data in a time-sharing manner based on a time after a certain period of time has elapsed from the rise of the fourth toggle in the S@ signal. 3) The memory control device according to claim 2, wherein a predetermined time from the rise of the fourth toggle in the @CAS@ signal is controlled by a counter. 4) A memory control device according to claim 2, wherein the control signal input to each memory is controlled by a transistor switch. 5) The memory control device according to claim 2, further comprising means for varying a certain period of time from the rise of the fourth toggle in the @CAS@ signal in accordance with the characteristics of the dynamic RAM. Characteristic memory control device. 6) A memory control device according to claim 5, wherein the variable means comprises a monostable multivibrator.