JPS6116347A - Memory scanner - Google Patents

Abstract

PURPOSE:To simplify the device constitution to reduce the cost by providing a logical operation means, update quantity output means, comparing means, etc. to generate successively memory addresses different from one another in a designated area. CONSTITUTION:A memory scanner is provided with latches LT1-LT7, logical arithmetic units ALU1 and ALU2, digital comparators DCP1 and DCP2, multiplexer MP1, buffers BF1 and BF2, control unit DEC, etc. A data line DATA and an address line MA are connected to the data line and the address line of a system, and the data line from the data output terminal of a memory is connected to a signal line Dout, and the control output terminal of the system is connected to a signal line LD, and a signal line HOLD is connected to the reference input terminal of the system. Control output terminals of the system are connected to control signal lines CP1-CP5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory scanning device that scans a predetermined area of memory specified by parameters of two or more dimensions.
In particular, the present invention relates to a memory scanning device capable of high-speed processing.

■Conventional technology For example, when processing two-dimensional image data or character pattern data, the position of each pixel is calculated and the data reading and data judgment are performed while determining whether the position falls within the processing range. and repeat these actions over and over again. This type of processing is relatively complex, so
It is often processed by a general-purpose microprocessor.

However, performing this type of repetitive processing in a microprocessor takes a very long time. Therefore, if you want to increase the processing speed, operations such as address calculation should be performed using multiplication, division, etc.
In many cases, a device configuration is used in which processing is performed by an advanced hardware arithmetic unit that includes functions such as various functional calculations, and the remaining processing is performed by a general-purpose microprocessor, etc., but this type of device has a complex configuration and is expensive. Moreover, since software processing is also included, the processing speed often does not improve much. 1゜ ■Object of the Invention The first object of the invention is to provide a device that performs high-speed memory scanning for a predetermined area expressed in two or more dimensions. The second objective is to simplify the device configuration and reduce costs.

■Structure of the Invention In order to achieve the above object, the present invention provides a logical operation means including relatively simple operation elements such as an adder, an update amount output means for outputting at least two types of address update amounts,
The apparatus includes a plurality of comparison means and the like for determining the end of scanning of each scanning axis of the scanning area, and sequentially generates mutually different memory addresses within the designated area. In other words, for example, if memory is allocated to two-dimensional coordinates, the memory addresses are continuous on one scanning axis (i.e., the main address), but are discontinuous on the other scanning axis (i.e., the secondary address), so the address When scanning continuous memory, the memory address is sequentially updated with the first update amount, and when the address reaches the scan end position, that is, a non-continuous address position, the memory address is updated with the second update amount.

By repeating these operations, two-dimensional memory scanning can be performed.

Note that the main address or the coordinates of the main scanning axis and the sub address or the coordinates of the sub-scanning axis in the present invention are determined depending on the configuration of the input device or output device of the system that requires memory scanning, and is selected by a combination of primary address and secondary address.

To perform this type of operation, at least one calculation means is required. However, even when using a presettable counter, there are two processes that require calculation: calculation of the address of a non-contiguous area and calculation of the scan end address of a continuous area, so there is only one calculation means. In this case, switching of the calculation target becomes complicated and the processing takes time. Therefore, in a preferred embodiment of the present invention, a first calculation means for calculating the scan end position of a scan area with consecutive addresses, and a second calculation means for generating address information to be given to the memory are provided. According to this, the processing procedure is simplified and the processing speed is also improved.

One possible use of memory scanning is, for example, detecting the start position of a character turn. In this type of use, the desired result is, for example, information on the position of the first black pixel that appears within the scanning range.

Therefore, in a preferred embodiment of the present invention, scanning is terminated when the data read from the memory reaches a predetermined value. According to this, since the memory address that satisfies the conditions, that is, the desired information is held inside the scanning device, some other additional circuits can be omitted in the above-mentioned applications.

Examples of the invention The present invention will be described in detail below with reference to one drawing.

FIG. 1 shows a memory scanning device embodying the invention. Referring to FIG. 1, this memory scanning device includes a latch L
TI, LT2. LT3. LT4゜LT5. LT6. L
T7. Logical operation units ALU1, ALU2. Digital comparators DCPI, DCP2. Multiplexer UPI, buffer (three-state output) BFI, BF2. It is equipped with a control unit DEC, etc.

When this memory scanning device is used as part of a predetermined system, the data line DATA and address line MA shown in the first part are connected to the data line and address line of the system, respectively, and are connected to the data output terminal of the memory. A data line of the system is connected to the signal line DOυt, a control output terminal of the system is connected to the signal line LD, and a signal line HOLD is connected to the reference input terminal of the system. Each control signal line CPI, CP2 . A control output terminal of the system is connected to CP3°CF2 and CF2.

FIG. 2 shows the flow of the operation of the apparatus shown in FIG. 1, FIG. 3 shows an example of the timing of each part of the circuit, and FIG. 4 shows the relationship between memory addresses and two-dimensional coordinates. This will be explained with reference to each figure.

When operating a memory scanning device, various parameters are first set. In this example, parameters include scan start addresses ST, A D, increment value INC, skip address value 5KIP, main scan address LEN, scan end address EDA'D, and mode set parameter of control unit DEC.

This mode set parameter ends scanning when the read memory data (Dout) becomes "1". Scanning ends when Dout becomes rOJ. and r) do not respond to the state of out; and select the scanning direction.

For example, if the memory address increases continuously to the right in the horizontal direction on two-dimensional coordinates and increases downward by a predetermined value (maximum coordinate value in the horizontal direction) in the vertical direction, Main scan all coordinates from left to right and sub scan from second to bottom! , the increment value INC is "1".
is set, and the skip address value 5KIP is the horizontal scanning width LE from the horizontal maximum value of the two-dimensional coordinates of the memory.
Set the value minus N.

When a high level H is applied to the load signal line LD after initialization, the memory scanning device starts operating. Subsequent control of each section is performed by signals from the control unit DEC.

First, multiplexer MPI is set to select input terminal A, that is, data 5TAD held in latch LTI, and the operation mode of logical operation unit ALU1 is set to (A+0). In this state, the logical operation unit ALUI outputs a value obtained by adding 0 to the scan start address 5TAD applied to its input terminal A to its output terminal OUT.

Here, one pulse is output to the signal line RD.

This causes the scan start address 5TA to be set in the latch LT6.
The value of D is set.

Next, set the operation mode of the logical operation unit ALUI to (A
10B). In addition, the logic operation unit ALU
Set the calculation mode of No. 2 to (A+B-1). In this state, the input terminals A and B of the logical operation unit ALU2
Since the main scanning address width LEN and the scanning start address 5TAD are respectively applied to the output terminal OUT of the ALU2.

A value of 5TAD+LEN-1 appears. Here, a launch pulse CP7 is output and its value is held by the launch LT7. This held value is applied to input terminal A of digital comparator DCP2.

Next, multiplexer MPI is set to select input terminal B, ie increment value INC.

Here, since the output data of the latch L T 6, that is, the generated memory address, is fed back to the input terminal B of the logic operation unit ALU, the logic operation unit ALU,l outputs the memory address that is currently being output. Outputs the value added with the increment value INC.

When the read pulse RD is output in this state, the generated address is updated to the output data of the logical operation unit ALUI, that is, the value obtained by adding the increment value INC to the value currently being output, and immediately after that, the value output by ALUI is updated to a value that further adds an increment value INC. Read pulse RD
is applied to the memory to be scanned along with the generated address information.

Therefore, in this state, the contents of the memory are read every time the read pulse RD is output, and the read address is updated by an increment value (+1 in this case) each time.

Repeat the above operation and the generated address will be 5 TAD + LE
'N, it is the output data 5TA of latch LT7.
Since it is larger than D+LEN-1, the digital comparator DC
P2 outputs a skip select signal 5SEL. When this signal appears, the control unit DEC sets the multiplexer MPI to select the skip address value 5KIP held in the input terminal C1, ie the latch LT3. As a result, the logical operation unit ALUI outputs a value obtained by adding the skip address value 5KIP to the currently output address 5TAD+LEN.

When the read pulse RD is output here, the value 5TAD+LEN+S is output from the logic operation unit ALU1.
K I P is applied to memory as a generated address. In other words, while scanning the memory in the horizontal direction, the address is incremented by 1 every time the read pulse RD is output, but when one line of scanning is completed, the skip address value 5KIP is added to it and the address is incremented by 1 in the vertical direction. Update coordinates (+l)L
, the horizontal coordinates are returned to the scanning start position.

As described above, the main scanning and sub-scanning of the memory are repeated. For example, when the control unit DEC is set to the mode of searching for data rlJ, the data (Dout) read from the memory becomes "1". At this time, the scan is considered to have ended. When scanning is completed, set the operation mode of the logic operation unit ALUI to (B+O),
The scan end signal HOLD is set to end the operation. The latch LT6 retains the address information at the time when the scan is completed, so if the output data of the logical operation unit ALUI is read out via the buffer BFI after the operation is completed, the data will be stored for the first time during the memory scan. 1" is found, the value of the address can be found.

If the preset data conditions are not met during scanning, the control unit DEC terminates the memory scanning by the signal vdetJC, which is output when the generated address exceeds the scanning end address EDAD, and the hold signal HOL
Output D.

In the above description, the continuous direction of the memory is set as the main scanning direction and the discontinuous direction is set as the sub-scanning direction, but these relationships can also be reversed. In that case, the increment value ING is
Set the same value as the maximum horizontal coordinate value XM of the memory, and set -XM(Y-1)+ to the skip address value 5KIP.
Set 1. (Y is the vertical width of the scanning area), and set the main scanning address width LEN to XM.(Y-2) to XM.(y
-1) Just set the value within the range of -1. In this case, the generated addresses are 5TAD and 5TAD+XM.

5TAD+2-XM, 5TAD+3=XM, -=--
・−・＝・−＝.

5TAD+('V-1)・XM, 5TAD+1.・
5TAD+1+XM.

5TAD+1+2・XM, 5TAD+1+3=XM,
It changes as ==..., EDAD.

Further, in the above description, the scanning direction is set in the direction of increasing the address, but it can also be set in the opposite direction.

That is, in the above case, the increment value INC is set to a positive value, but if it is set to a negative value, the scanning direction is reversed. However, in the above operating mode, the digital comparators DCPI and D
The signal obtained from the output terminal A<B of CP2 was referred to, but if the scanning direction is reversed, it is necessary to monitor the signal from the output terminal A>B. These signals are automatically selected by the control unit DEC depending on preset parameters.

In the above embodiment, two logic operation units ALU]
, , ALU2 are used, but it is also possible to combine these into one. In that case, for example, a counter with a recent function is provided in place of the logical operation unit ALUI shown in FIG. Then, the scan start address 5TA is sent to the preset data terminal of the counter via a multiplexer.
D and one of the output signals of the logic operation unit ALU2 is applied, and the read pulses R and D are configured to count up (or count down). However, with this configuration, it is difficult to switch the output of the logical operation unit ALU2 and generate the latch timing, and in particular, when switching between the main scanning direction and the sub-scanning direction, it is necessary to switch the ALU2 frequently. There is a possibility that the circuit configuration becomes complicated and the scanning speed becomes slow.

(2) Effects of the Invention As described above, according to the present invention, high-speed memory scanning can be performed with a simple circuit configuration. Note that the logical operation means used in the present invention may be a simple one having at least an addition function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one type of memory scanning device embodying the invention. FIG. 2 is a flowchart showing the operating order of the apparatus shown in FIG. FIG. 3 is a timing chart showing an example of signal timing of the device shown in FIG. FIG. 4 is a plan view showing the relationship between memory addresses and two-dimensional coordinates. ALUI: Logical operation unit 7 (address information generation means) ALU2: Logical operation unit (logical operation means) MP
I: Multiplexer (update amount output means) LT6: Latch (first data holding means) LT7: Latch (second data holding means) DCP2: Digital comparator (first comparing means) DCPl: Digital comparator (first comparing means) 2 comparison method) LT
5: Latch (third data holding means) DEC: Control Uniso 1- (electronic control means) BFI, BF2: Vanofa

Claims (4)

[Claims] (1) Address information generation means for generating memory scanning address information including a main address and a sub address; at least two
Update amount output means for applying different types of address update amounts to the address information generation means; first data holding means for holding output data of the address information generation means; logical operation means for generating scan end address information of the main address; A second data holding means for holding the output data of the calculation means; A first comparison means for comparing the output of the address information generation means and the output of the logical calculation means; A third data holding means for holding at least scan end address information of the sub-address. a data holding means; a second comparing means for comparing the output of the address information generating means and the output of the third data holding means; and controlling the update amount outputting means according to the comparison result of the first comparing means; A memory scanning device comprising: electronic control means for sequentially updating address information generated by the address information generation means until a predetermined condition is met. (2) The memory scanning device according to claim (1), wherein the address information generating means is a second logic operation means. (3) The predetermined conditions include that the output of the first comparison means has become a predetermined state, that the output of the second comparison means has become a predetermined state, and that the data read from the memory The memory scanning device according to claim 1, further comprising at least one of: reaching a predetermined value. (4) The update amount output means includes two data holding means,
3) The memory scanning device described in section 3).