JPS60181930A - Microprogram controlling system - Google Patents

Abstract

PURPOSE:To speed up an instruction executing time, and to execute a control at a high speed by executing in parallel a read-out access of the next instruction in case when a condition is not formed, and a read-out access of a branch destination instruction in case when the condition is formed, by executing a condition branch type instruction. CONSTITUTION:A microprogram of the same contents is stored in a main control storage 1 and a sub-control storage 2, respectively. Under a control of an execution timing controlling circuit 9, an instruction address register 7 sends out an address of the microprogram to the main control storage 1, and the first instruction which has been read out is sent out to a multiplexer 3. Also, an instruction register 4 inputs said first instruction, and its instruction is executed by an execution control part 5. As soon as an execution of this instruction is started, the next address is set to the register 7 through a multiplexer 8, and an access of the second instruction is executed in parallel to the execution of said instruction. In this way, whether a branch condition is formed or not is decided, and immediately after that, the next instruction can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Branch Field of the Invention The present invention relates to a microprogram control method that can perform high-speed access to microprograms, that is, instructions, and particularly to a high-speed access when the condition of a conditional branch type instruction is satisfied. The present invention relates to a microprogram control 311 method to be implemented.

(b) Prior Art and Problems Microprogram control methods, particularly methods for controlling the instruction execution sequence, can be broadly classified into two types. One is a method in which the instruction itself read from the control memory includes a field indicating the address in the control memory where the next instruction to be executed is stored. The other is that a normal instruction does not include the address in control memory where the next instruction to be executed is stored, and in this case, the address of the currently executing instruction is +1. This is a method in which the address is set as the next execution address and the branch destination address is given to a predetermined field in the instruction only when branching the sequence. In the latter method, the address of the current instruction is usually +1 during the execution time of the current instruction.
Then, the control memory is accessed in parallel to retrieve the next instruction, but in the case of a conditional branch type instruction, a branch/non-branch decision is made during the execution of the instruction. Therefore, when a branch is made due to the establishment of a condition, the operation that has already accessed the control memory as described above is wasted, and it is necessary to access a new address of the branch destination in the control memory from this point onwards. Therefore, when branching with a conditional branch type instruction, the instruction takes longer to execute than other instructions.

Furthermore, in order to access a new address in the control memory when a condition is met, the execution timing of this instruction must be controlled separately from other instructions, which makes the hardware complicated. Furthermore, the slower the access speed of the control memory, the longer the execution time when the condition of the conditional branch instruction is satisfied, so there is a disadvantage that the use of an economical low-speed memory increases the difference in execution time.

(C) Object of the Invention In view of the above drawbacks, the object of the present invention is to provide a microprogram that enables high-speed control so that the execution time of a conditional branch type instruction is not slower than that of other instructions. The objective is to provide a control method.

(d) Structure of the Invention The structure of the present invention consists of a first and a second device storing a microprogram.
a control memory, a selection means for selecting the instruction read from the second control memory, a register for storing the instruction selected by the selection means, and a control memory for selecting the instruction read from the second control memory; a first address sending means for sending an address of an instruction to be executed next to a first control memory; and a branch destination address to the first address sending means when the instruction stored in the register is a branch instruction. a second address sending means for sending an address to be executed next in the second address sending means;
means for sending a branch destination address to a second control memory; when the branch condition of the instruction stored in the register is met, the selection means selects the instruction read from the second control memory;
Subsequently, the second address sending means selects the instruction read from the first control memory at the address sent, and when the branch condition is not satisfied, the selection means selects the instruction read from the first control memory. It is.

(e) Embodiments of the Invention When executing a conditional branch type instruction, the present invention provides a conditional small I'l
An access to the control memory for reading the next instruction that occurs in the case of , and an access to the control memory for reading the instruction at the branch destination that occurs when the condition is satisfied are performed in parallel. In order to enable this parallel access, there are two types of access: one when the condition is not met, and one when the condition is met.
A system access system is provided, and the access system for the control memory is duplicated. When the condition is determined, the instruction obtained from the corresponding access system, depending on whether the condition is satisfied or not, is taken into the instruction register as the next instruction to be executed. This duplexed access system may simply be a duplication of control memory, for example.

The figure is a block diagram of a circuit showing one embodiment of the present invention.

The microprogram is the main control record 1. It is stored in a1.

The sub-control memory 2 stores microprograms having the same contents as the main control memory 1. Under the control of the execution timing control circuit 9, the instruction address register 7 sends the address of the instruction part, ie, the microprogram, to be executed to the main control memory 1, and the first instruction read from the main control memory 1 is sent to the multiplexer 3. be done. The execution timing of the instruction is given from the execution timing control circuit 9 to the instruction register 4, and the instruction register 4 takes in the first instruction from the multiplexer 3. The first instruction taken into the instruction register 4 is A.
It enters the execution control unit 5 via , is decoded, and the contents of the instruction are executed. Simultaneously or immediately after the start of execution of this instruction, an update pulse is sent to the instruction address register 7 of the execution timing control circuit 9, and the next address obtained by the +1 circuit 10 is sent to the instruction address register 7 via the multiplexer 8.
cents. As a result, the next instruction, that is, the second instruction, is accessed to the main control memory 1 in parallel with the execution of the instruction.

If the instruction sent to the instruction register 4 is a conditional branch type instruction, the information in the condition specification field of the instruction is decoded by the execution control unit 5 and the condition is determined.

The branch destination address when the condition is met is sent from the instruction register 4 via B to the sub control memory 2, and the branch destination instruction is accessed. At the same time, as described above, the address of the second instruction is sent from the instruction address register 7, and the instruction access when the condition is not met is the main control register 1. ! 1. Here, when the condition determination in the execution control section 5 is completed, a determination signal is sent to the multiplexer 3. Multiplexer 3 outputs sub-control memory 2 when the condition is met.
The branch destination instruction is selected and sent to the instruction register 4, and if the condition is not satisfied, the second instruction from the main control memory 1 is sent to the instruction register 4. Therefore, as soon as it is determined whether the condition is met or not, execution of the next instruction can begin immediately.

When the branch destination instruction is executed when the condition is satisfied, the next address is specified by the +1 circuit 6 and sent to the multiplexer 8 as the branch destination address. Execution timing control circuit 9
By the multiplexer 8 switching signal, this address is stored in the instruction address register 7 when the branch condition is satisfied, and updated to an address that is +1 to the branch destination address. Therefore, after a branch, the execution control unit 5 can read instructions consecutive from the branch destination address from the main control memory 1 and execute them.

In this embodiment, the main control memory 1 and the sub-control memory 2 are the same, but the sub-control memory 2 has a relationship between branch address and branch destination instruction contents such that only the instruction at the branch entry address is output. A similar effect can be obtained with tabled memory.

(f) As described in the detailed description of the invention, at the time when the condition determination is made, the present invention
Because the next instruction to be executed is immediately obtained depending on whether the condition is satisfied or not, the instruction execution time is faster than the conventional method in which access to the instruction at the branch destination address is started from the moment it is determined that the condition is satisfied. can be converted into Furthermore, the timing of instruction execution control can be simplified. Furthermore, since the execution time is the same for conditional branch type instructions and other instructions, there is no difference in instruction execution time even if an economical low-speed memory is used for control storage, which is advantageous. If a large-capacity one-chip memory or the like is used, the amount of additional hardware can be reduced.

[Brief explanation of the drawing]

The figure is a block diagram of a circuit showing one embodiment of the present invention. 1 is a main control memory, 2 is a sub-control memory, 3 and 8 are multiplexers, 4 is an instruction register, 5 is an execution control unit, 6 and 10 are +1 circuits, 7 is an instruction address register, and 9 is an execution timing control circuit. .

Claims (1)

[Claims] a first and second control memory storing a microprogram;
a selection means for selecting an instruction read from the second control memory; a register for storing the instruction selected by the selection means; and a first control when the instruction stored in the register is a non-branch instruction. A first address sending means that sends the address of the next instruction to be executed to the memory, and when the instruction stored in the register is a branch instruction, the first address sending means sends the address of the next instruction to be executed at the branch destination address. and means for sending a branch destination address to the second control memory, and when the branch condition of the instruction stored in the register is met, the selection means Second
select the instruction read from the control memory of the second
The instruction read out from the first control memory is selected at the address sent by the address sending means, and when the branch condition is not satisfied, the selection means selects the instruction read out from the first control memory. Microprogram control method.