JPH0261725A - Micro branch system - Google Patents

Abstract

PURPOSE:To quickly perform the processing by providing a control storage capable of simultaneous access of two data and a selector which selects either of data to read the micro instruction code in the branch destination. CONSTITUTION:When a branch instruction is executed, a control storage (CS) address 10 is outputted from a microprogram counter (MPC) 5. A CS 1 is retrieved by this address, and a micro instruction code R of the sequential address is outputted from an output signal line 21 of a port A and is supplied to a selector 6. In this case, the value of the branch destination address is outputted from an RDR 2 to a signal line 31 of a branch destination address part simultaneously and is supplied to the CS 1 and the MPC 5. The micro instruction code is outputted to the selector 6 in accordance with this address. A branch success/failure signal 70 is outputted from a branch deciding part 4 to the MPC 5 and the selector 6 and is used as a selector signal of either micro instruction code.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a microbranch method used in a microprogram processing type information processing device, and particularly relates to a microbranch method used in an information processing device using a microprogram processing method. The present invention relates to a micro-branch method that can realize faster processing speed only by shortening the basic clock, as a configuration that allows reading out a branch destination micro-instruction code without changing the address of the micro-instruction code.

(Prior Art) FIG. 4 shows a configuration example of a circuit for controlling branching of microprogram processing used in a conventional information processing device.

Further, part of the flow of the microprogram processing executed in the above-mentioned Fig. 4 is shown in Fig. 3, and the timing of data changes in each part in the above-mentioned Fig. 4 is shown using broken lines in Fig. 2. ing.

A conventional microprogram processing means including branch instruction processing will be explained using the above figures.

First, when executing the process at address 300 in FIG.
Micro program counter (hereinafter referred to as MPC) shown in the figure
The value of 04 is "300". This data 010 of MPCO4 specifies the address of control memory (hereinafter referred to as C8) 01 that stores the microprogram, that is, the microprogram execution address, and by specifying the same address, the cso
The data read from t is transferred to register (hereinafter referred to as RDR) 02. RD R02 is a register that latches the output data 020 of C3OI. The data 030 (-microinstruction code) latched in the RDRO2 is decoded into a signal group 050 by the decoder (DRC) 03, and these decoded output signals 050 are sent to each control section.

Thereafter, each control unit proceeds with the process.

Here, the processing content at address 301 in FIG. 3 is branch condition F1.
is satisfied, the process is moved to address 310, and branch condition F
If 1 is not established, step 302 is executed.

To explain this operation, the microinstruction code (hereinafter referred to as R (address)) read from RD R02 in FIG. Output.

The branch determination unit 05 receives the branch instruction signal 040 and selects the designated branch condition F1 from the branch conditions 060.

Then, it is decided whether to branch or not, and when branching (30
If the condition is met at address 1), the branch signal 070 is set to M.
Output to PCO4.

On the other hand, in the microinstruction code on the RDRO2, the address part 031 that specifies the branch destination address (310'') is output to the MPCO4, so the MPC04 uses the branch signal 070 as an enable signal and uses the branch destination address (hereinafter referred to as BRA) as an enable signal. ) is generated as CS address 010 and c
Output to sot. As a result, C3OI is R(BRA
) and RD R02 reads R(BRA), thereby executing the microinstruction at the branch destination.

Next, according to the timing chart of FIG. 2, a description will be given of the process from execution of a branch instruction to execution of a branch destination microinstruction.

First, while executing the microinstruction at address 299 in Figure 3, the MPCO4 outputs the value "300", which is the count up of "299", as CS address 010, as shown by the broken line in Figure 2. . With this address 010, C5OI is set to 02 as data, as shown by the broken line in Figure 2.
0, R(300) is output.

Next, if the data changes at the rising (or falling) of the basic clock, at point A in Fig. 2, at point A in Fig. 3,
The processing at address 99 is completed, and the processing in which data (microinstruction code) 030 is output from the RDRO 2 and decoded by the decoder 03 begins.

At the same time, MPCO4 counts up the value "30".
1' as the CS address O1O, thereby
R (301) is output from 3OI as data 020.

Similarly, processing at address 301 in Figure 3 is started at point B in Figure 2, and MPCO4 is counted up to the value "302".
is output as CS address 010. This allows C5
R(302) is output as data 020 from the OI, but at this time, since R(301) is a branch instruction, a branch is determined, and the branch determination unit 05 outputs a branch signal 070 shown by a broken line in FIG. is output, MPCO4 outputs RD R0
Read data 031 of the address part from 2, generate branch destination address BRA, output it again to C3OI as CS address 010, and before the processing of R(301) is completed, search C5OI again and write R(310). ) was being output again.

As a result, RD R02 reads R(310),
The branch destination microinstruction can be executed at point D.

(Problem to be Solved by the Invention) As described above, conventionally, during the execution of a microinstruction that includes a branch instruction, the address of C8 is changed from a sequential address to a branch destination address. ) decision will be delayed. Therefore, it has been difficult to increase the processing speed simply by shortening the basic clock.

The present invention has been made in view of the above-mentioned embodiments, and enables reading of a branch destination microinstruction code without changing the address of control memory (CS) during execution of a branch instruction, thereby increasing processing speed by shortening the basic clock. The purpose is to provide a microbranch method that can achieve high speed.

[Structure of the invention] (Means and effects for solving the problems) The present invention has the following features:
A two-port control memory (CS) that can access two pieces of data at the same time and a selector that selects one of the simultaneously accessed data are provided to allow branching without changing the address of the control memory during execution of a branch instruction. This makes it possible to read the previous microinstruction code. This eliminates the need to change the control memory address while executing a branch instruction, making it easy to increase processing speed simply by shortening the basic clock. Can be done.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In Figure 1, ■ is 2 that stores the microprogram.
This is a control memory composed of RAM (ROM) of the port, and is hereinafter referred to as C8. 2 is a register that latches the output data (microinstruction code) of C8I, hereinafter referred to as RD.
It is called R. 3 is a decoder (DCR) that decodes the data of RDR2, that is, the microinstruction code. 4 is a micro address counter (MPC) which receives a branch instruction signal 40 and a branch condition 60, determines whether the condition is satisfied or not, determines whether to branch, and outputs the resulting signal 70, which will be described later.
5 and selector 6. 5 is a micro address counter which receives the signal 70 from the branch judgment unit 4 and outputs the CS address IO, hereinafter referred to as MPC.
It is called. A selector 6 selects either the microinstruction code R (BRA) of the branch destination address or the microinstruction code R (SEQ) of the sequential address in response to the signal 70 from the branch determination unit 4.

FIG. 2 is a flowchart showing the data transition states of each section in FIG. 1 in comparison with the conventional example having the configuration shown in FIG. 4 (the conventional example is indicated by broken lines).

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 to 3.

When a branch instruction like the one at address 301 in Figure 3 is executed,
The value counted up from MPC5 is CS address 1
Output as 0. With this CS address 10, C8
1 is searched and the sequential address microinstruction code R (S
EQ) is output and supplied to the selector 6. On this occasion,
At the same time, the value of the branch destination address is output from RDR2 to the signal line 31 of the branch destination address section, and the value of the branch destination address on this signal line 31 is supplied to C81 and MPC5.

C3I is searched by this branch destination address, and C81
The microinstruction code R (BRA) of the branch destination address is output from the output signal line 22 of the B port of the microinstruction code R (BRA), and is supplied to the selector 6.

Also, as in the past, the microinstruction code 30 read from the RDR 2 is decoded by the decoder 3, and the branch decision unit 4 outputs a signal 70 indicating whether the branch is taken or not taken, to the MPC 5 in accordance with the branch instruction signal 40. But this signal 70
is also supplied to the selector 6 at the same time, and is used as a selector signal to select either one of the microinstruction codes R(SEQ) and R(BRA) supplied to the selector 6.

As a result, if the branch is taken, the microinstruction code R (BRA) of the branch destination address is output from the selector 6 as the output data of the selector 6. However, in this case, MP
C5 outputs the value of "BRA+1" in synchronization with the clock, and supplies it to C8l as a CS address IO. Therefore, during execution of a branch instruction such as at address 301 in FIG. 3, the branch destination address BRA is not output to C8l.

The timing chart in Figure 2 shows the changes in each data when the process is executed according to the flowchart in Figure 3 and a branch is established with the branch instruction at address 301. to point D. Also,
When the microinstruction code from point A to point B in Figure 2 is not a branch instruction (such as address 300 in Figure 3), the data on the output signal line 22 of the B port of C8l is used to specify the branch destination address. This is the value that is obtained by outputting the data of the micro field that has been set to the signal line 31 of the branch destination address section and searching for C81, but since the signal 70 indicating whether the branch is taken or not taken does not indicate that it is taken, it is not selected. There isn't, so it's not a problem.

As described above, according to the embodiment of the present invention, the branch destination microinstruction code can be read without changing the address of the control storage unit during execution of the branch instruction. By eliminating the time constraints on the basic clock caused by changing the C3I address from a sequential address to a branch destination address in a microinstruction, it is possible to speed up the basic clock, which only shortens the basic clock. The microprogram processing speed can be increased.

[Effects of the Invention] As detailed above, according to the microbranch method of the present invention, there is provided a two-port control storage unit that simultaneously outputs a microinstruction code of a sequential address and a microinstruction code of a branch destination address, and a selector that selects one of the microinstruction codes outputted from the storage section; a register that stores the microinstruction code outputted from the selector; and a decoder that decodes the microinstruction code stored in the register; A branch determination unit receives a specific output signal of this decoder and a branch condition given from the outside and determines whether the branch condition is satisfied or not, and a signal representing the determination result of this branch determination unit is supplied to the selector as a selection signal. and a circuit for supplying the branch destination address of the microinstruction code stored in the register to the control storage section, and the circuit supplies the branch destination microinstruction address of the microinstruction code stored in the register to the control storage section without changing the address of the control storage section during execution of the branch instruction. By adopting a configuration in which code is read, processing speed can be increased simply by shortening the basic clock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the data transition state of each part in FIG. 1, and FIG. 3 is a microprogram for explaining the operation of the above embodiment. FIG. 4 is a block diagram showing a conventional microprogram control mechanism. 1...C8 (control storage unit), 2...RDR (register for storing microinstruction code), 3...decoder (
DCR), 4... Branch determination unit, 5... MPC (micro program counter), 6... Selector, 1o
...CS address, 21...A port output signal line, 22...B port output signal line, 31...signal line of branch destination address section. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (1)

[Claims] a two-port control storage unit that simultaneously outputs a microinstruction code of a sequential address and a microinstruction code of a branch destination address; a selector that selects one of the microinstruction codes outputted from the control storage unit; A register that stores the microinstruction code output from this selector, a decoder that decodes the microinstruction code stored in this register, and a branch condition that receives a specific output signal of this decoder and a branch condition given from the outside. a branch determining unit that determines whether the branch is taken or not; a circuit that supplies a signal of the determination result of the branch determining unit to the selector as a selection signal; and a control storage unit that stores the branch destination address of the microinstruction code stored in the register. A micro-branch method characterized in that the branch destination micro-instruction code is read out without changing the address of the control storage unit during execution of the branch instruction.