JPS5882342A - Microprogram controller - Google Patents

Abstract

PURPOSE:To perform high-speed loop execution while decreasing the number of microinstruction steps in a loop by storing microinstructions in the loop after execution in a queue mechanism in the order of the execution, and fetching the microinstructions from the queue mechanism during the loop execution. CONSTITUTION:After a loop condition field is decoded by a decoder 7, a loop discriminating circuit 9 discriminates on whether a specified status is set or not and when a discrimination on loop continuation is made, a queue mode flop (QMF)10 is set to ''1'' to set a microinstruction in a register (MIR)5. Then, an MIR input selector 6 selects a readout line from a microinstruction queue (MIQ)4 to fetch the microinstruction from the MIQ4, and a hop counter 11 goes up by ''1'' when the instruction is fetched from the MIQ4. Thus, a discrimination on loop conditions is made by the microinstruction from the MIQ4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used in a data processing device, and is designed to reduce the number of microsteps in a loop, particularly in response to a microprogram-intensive device designed to perform loop execution in a vertical microprogram. , and it is intended to enable loop processing to be performed quickly without fetching microinstructions directly from the external memory T, m i .

Conventionally, in the loop execution of a vertical microprogram in a microprogram control device, the number of bits of a vertical microinstruction (usually about 16 bits) is limited, so the loop condition must be determined in the final step of the loop. If the loop has not finished, return to the first step of the loop, and if the loop has finished, put a condition branch instruction that executes the next microinstruction, or unconditionally insert the jlti-first of the loop in the final step A branch instruction is placed to return to the step, and there is a condition branch instruction within the loop to determine the loop condition, and depending on the end of the loop, execution of the ninth microinstruction is executed (i'l).

However, the condition branch #: condition branch instruction placed in the final step of these loops is unrelated to the operation within the loop, and there is a drawback that the loop execution is processed in one step more than the actual operation. Furthermore, when a loop is executed, each microinstruction within the loop is fetched from the external storage device for the number of times the loop is executed, so there is also the drawback that a wasted instruction fetch cycle is executed.

The purpose of this invention is to store microinstructions that have completed execution within a loop in a queue mechanism in the order of execution, and to eject microinstructions from the queue mechanism during execution of the loop, thereby preventing instructions from being fetched from an external storage device. If the loop processing is performed without executing the above command, and the loop termination condition is not satisfied after determining the loop condition, it is possible to use a field of several bits to instruct the instruction to be fetched from the queue mechanism, or other operations. It is an object of the present invention to provide a microprogram control device that executes this instruction in the same step as the above, reduces the number of microinstruction steps in a loop, and quickly processes a loop execution instruction.

According to the present invention, there is provided a microinstruction queue mechanism for accommodating microinstructions that have completed execution in a selected number of steps in execution order during loop execution in a microprogram, and means for storing each microinstruction in the loop that has completed execution in the queue mechanism; A loop 161 control means for determining a loop condition when executing a microinstruction indicating a loop end condition and controlling whether to take out the microinstruction from the queue mechanism or the next microinstruction from the external storage device. , handles loop execution within the queue mechanism.

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the microprogram control device of the present invention includes an interface bus 1 with an external storage device (not shown), a microsequencer (MSQ) 2 for controlling the sequence of microprograms, A microprogram counter (MPC) 3 existing in a micro sequencer (MSQ) 2, a microinstruction queue (MIQ) 4 that collects 8 steps of microinstructions that have completed execution during loop execution, and a microinstruction queue (MIQ) 4 that collects instructions that have been executed during loop execution Microinstruction register (MIR) containing 5
9, the input of the microinstruction register (MIR) 5 is taken out from the external storage device or the microinstruction queue (MIQ'
) 4, a decoder 7 that decodes the microinstruction stored in the microinstruction register 5, a current instruction register (CIR) 8 that stores the decoded signal, and a loop termination condition. a queue mode flop (QMF) 10 that indicates that a microinstruction in the microinstruction queue (MIQ) 4 is being executed; It is composed of a pop counter (POC) 11 that indicates the output address, and a bush counter (PUC) 12 that indicates the input address in the microinstruction queue (LV[IQ) 4.

In the normal execution of a microinstruction in the present invention, a microinstruction is fetched from an external storage device according to an address determined by a microphone sequencer (MSQ') 2 and stored in a microinstruction register (MIR') 5. MIR5
The K stored microinstructions are decoded by the decoder 7 and sent to the current instruction register (CIR) as control signals for each part.
The command is stored in CIR8, and the command is executed according to the instruction of the control signal of CIR8. Instruction addresses other than branch-related instructions are determined by the contents of a microprogram counter (MPC') 3, and microinstructions are sequentially fetched from an external storage device and executed.

This example assumes a vertical microinstruction [2. Pipeline control is performed at the following stages of instruction fetch (setting the microinstruction to MIR5), decoding (decoding the contents of MIR5 and setting it to ClR8), and instruction execution. I am doing it. An example of a four-step loop in this embodiment is shown in FIG. 2A, and a loop execution time chart of pipeline control in the three stages is shown in FIG. 3A.

Microinstruction a2 sets initial values of loop conditions such as the number of loops, and clears bush counter (PUC) 12. POCl2 in this embodiment is a 3-bit counter, and is incremented by 1 each time a microinstruction from MIR5 is stored in microinstruction queue (MIQ) 4. When 8 steps of microinstructions are continuously stored in MIQ4, POCl2 becomes all "1".
MIQ4 is held in this state, and MIQ4 enters a state in which it is prohibited to enter. This write system halt state can be detected by the PUC12 using a microinstruction.
When cleared, it is released and the micro ordinance is stored in MIQ d again.

Microinstructions b2 and c2 following microinstruction a2
performs the indicated operation, and PUC12
1 is stored at the address in MIQJ indicated by . Further, the next microinstruction d2 is an instruction that simultaneously judges the loop end condition and determines whether to take out the microinstruction from within MIQd or to take out the next microinstruction from the external storage device. As is clear from FIG. 3A, when the next microinstruction e2 is being decoded, the next instruction is fetched from the external storage device or the microinstruction b2 from MIQ4 is stored in MIR5 at the same time. Loop condition determination must be performed using microinstruction d2.

Also, while executing the microinstruction d2, the pop counter (PO
C) 11 clearing is performed. The microinstruction d2°e2 is also stored at the address in the MIQd indicated by the PUC 12, similar to the microinstruction b21c2.

The first loop execution is executed by fetching an instruction from an external storage device in the same way as normal microinstruction execution. PUC12 is cleared by executing microinstruction a2, and MIQ4 is in a convolutional state, so the next microinstruction is M in the order of b21 ax r dB + 83.
Stored in IQ4.

In the microinstruction d2, after the loop condition field is decoded by the decoder 7, the loop judgment circuit 9 decodes the loop condition field.
Determine the success or failure of the instruction status (loop counter zero detection, etc.), and if the loop continues, set queue mode 70 (QMF) 10 to '1#, set microinstruction e2 to MIR5, and then , MIR input selector 6 selects the read line from MIQ 4 and PO
Since CLL is cleared, microinstruction b2 is M,
Extracted from within IQd.

POCII is incremented by 1 when an instruction is fetched from MIQ4. In this way +1.4IQ4
Microinstructions b2 + 02 r d2 are taken out one after another from microinstruction d2, and the loop condition is determined again with microinstruction d2, and when the loop end condition is met, the queue mode flop (QMF) 10 is reset to 0''.QM
When FIO is '1m, micro program counter (MP
C) 3 holds the next address of the microinstruction e2, and the next instruction f2 is read onto the interface bus 1 from the external storage device. When QMFIO becomes 0'', microinstruction e2 is followed by interface bus 1.
The instruction (instruction f++ following microinstruction e2) that had been read out is set in MIR5, and the bold state of microprogram counter (MPC) 3 is also released, returning to the normal instruction execution mode.

Since the loop condition determination of the microinstruction d2 in this embodiment does not require branch destination address information, which is conventionally necessary, even a vertical microinstruction can be executed in the same step as other operations. In the conventional loop execution of a microprogram, a condition branch instruction ft was required as shown in FIG. can.

As shown in Figure 3, fetching instructions from an external storage device requires at most two clocks, whereas setting instructions from microinstruction queue (MIQ) 4 to MIR5 can be executed in one clock. During loop execution, there is no unique free time in the shaded area in the time chart, and ideal pipeline control can be achieved. Figure 3B shows that the microinstruction queue (MIQ) 4 is not used and everything is stored in an external storage device. A time chart of a conventional method in which data is read from the memory and executed in a loop is shown.

Comparing this with the loop execution time chart in Fig. 3 A (!
By using this embodiment, a loop that used to be executed in 7+4 (N-1) clocks (N is the number of loops) can be executed in 7+4 (N-1) clocks (N is the number of loops), and the loop execution speed 1& can be more than doubled. can.

In addition, in FIG. 3, it takes two clocks to fetch a microinstruction from an external storage device, but if a memory with a slow access time is used, this embodiment will have a greater effect on the VC.

As explained above, the present invention reduces the number of microinstruction steps in a loop by providing a microinstruction queue mechanism for accommodating executed microinstructions during loop execution in the macro program control device. This has the effect of enabling high-speed loop execution without fetching instructions from the external storage device 7M.

[Brief explanation of drawings]

Figure 1 is the back of this older brother, a block diagram with all the examples, Figure 2 A is a flowchart of the 4-step loop in implementation 11 of this invention, Figure 2 B is the correspondence of the @ rice method. Loop flowchart, Figure 3 A, BI''i respectively 2
3 is an execution time chart corresponding to figures A and H. 1... Interface bus with external storage device, 2...
・Micro sequencer (MSQ), 3...Micro program counter (MPC), 4...Micro instruction queue (MIQ), 5...Micro instruction register (MI
R), 6... MIR input selector, 7... Decoder, 8... Current instruction register (CIR), 9...
Loop judgment 1 ('1 path, 10... Queue mode flop (QMF), 11... Hop counter (POC)
, 12... Bush counter (PUC). lPatent Applicant: NEC Co., Ltd. Agent AiL No.

Claims (1)

[Claims] When a loop in a microprogram is executed, a microinstruction queue mechanism accommodates each microinstruction that has completed its execution in a plurality of steps in the order of execution, a means for storing the microinstruction that has completed its execution in the queue mechanism, and a loop termination condition. A microprogram control device comprising: loop control means for determining a loop condition during execution of a microinstruction and controlling whether the microinstruction is taken out from the queue mechanism or the next microinstruction from an external storage device.