JPH05120080A - Firmware execution history storage system - Google Patents

Abstract

PURPOSE:To improve the coverage rate of operation at the time of the debugging of firmware by leaving history about the branch of a jump instruction too, as the history of the execution of the firmware. CONSTITUTION:An address register 3 fetches an instruction address a processor 1 executes, and the address register 4 fetches the instruction address executed one step before the instruction address. An arithmetic circuit 5 subtracts the output of the address register 4 from the output of the address register 3, and if this result is +1, a calculated output signal 501 is made logic '1'. Storage circuits 7 to 9 are constituted of the memories of the same address capacity as an instruction storage circuit 2 and of the data width of 1-bit. The signal of logic '1' of a data line 502, the calculated output signal 501 of the arithmetic circuit 5, and the signal obtained by inverting the logic of the signal 501 are written in the storage circuits 7 to 9. For instance, the address in which '1' is written as the data of the storage circuit 9 shows that it jumps without going forward to the address next to this address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a firmware execution history storage system.

[0002]

2. Description of the Related Art Conventionally, execution of firmware is recorded by writing a logical "1" into the data of the address when the firmware has a storage circuit having the same address capacity as the instruction storage circuit and data of 1-bit width. Was there.

[0003]

In this conventional firmware execution history storage system, it is possible to judge whether or not the firmware has passed through that address, but the instruction at the address next to the conditional jump instruction is shrunk from another address. In this case, it is not possible to determine whether the address has been passed because the conditional jump instruction was not satisfied and the address has advanced to the next address, or the address has jumped from another address above. There was a problem that it was insufficient to check the coverage of operations during debugging.

[0004]

A firmware execution history storage system of the present invention includes an instruction storage circuit for storing instructions executed by a processor, a first address register for storing an address executed by the processor, and A second address register for storing an address executed one instruction before the instruction indicated by the first address register; an arithmetic circuit for arithmetically operating output data of the second address register and the first address register; A first storage circuit having the same address capacity as the instruction storage circuit and a 3-bit input / output data width, and an instruction control circuit for issuing a storage instruction to the first storage circuit according to an instruction from a processor. The output data of the second address register is connected to the address line of the first memory circuit, and
"1" on the 3-bit input data line of the memory circuit
1 bit of the signal is connected to the operation output signal of the operation circuit and the inverted signal of the signal, and the execution clock supplied to the processor is the first address register, the second address register, and the second address register. 1 is connected to the write signal of the memory circuit.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, the processor 1 outputs the address to be executed to the instruction address 101, receives the instruction from the instruction bus 201 of the instruction storage circuit 2, and receives the clock 00.
The instruction is executed by 1.

When the history of the execution address of the instruction is stored, the processor 1 issues an instruction to the instruction control circuit 110 by the instruction signal 102. The instruction control circuit 110 outputs the write signal 111 every time the clock 001 is transmitted.

The memory circuits 7, 8 and 9 are composed of a memory having the same address capacity as the instruction storage circuit 2 and a data width of 1 bit, an address is indicated by an address 121, an operation output signal 501 and a data line 502. Is input data and is written by the write signal 111.
The data line 502 is always logic "1".

The address register 3 writes the instruction address executed by the processor 1, and the address register 4 writes the instruction address executed one step before the write signal 111.
Take in by. Further, the arithmetic circuit 5 is the address register 3
The address register 4 is subtracted from the result, and when the result is +1, the operation output signal 501 is set to logic "1".

The read control circuit 6 reads the data from the memory circuits 7, 8 and 9 when reading data 1
12, an address 602 output from the read control circuit 6 by using the select signal 601
Is applied to the memory circuits 7, 8 and 9.

Now, consider a case where an instruction as shown in FIG. 3 is stored in the instruction storage circuit 2 while the instruction signal 102 is instructed to store a history of instruction addresses by the processor 1.

NEXT in FIG. 3 indicates that after the instruction is executed, the program advances to the next address, and the condition JUMP (n +
2) indicates an instruction to jump to address n + 2 when a certain condition is satisfied.

It is also assumed that the address advances as shown in FIG. In this case, the operation is performed as shown in the time chart shown in FIG. 5, and as a result, the data is written in the memory circuits 7, 8 and as shown in FIG.

An address in which "1" is written as the data of the memory circuit 7 indicates that the processor 1 has executed the instruction of the address, and "0" indicates that the address is not executed. .. Where "1" is written as the data of the memory circuit 8, it indicates that the address (address + 1) has been advanced to the address indicated by it, and if "0", it does not proceed to the next address. Indicates that you jumped to. An address in which "1" is written as the data of the memory circuit 9 indicates that the address jumps without advancing to the next address.

Although not shown, when the memory circuits 8 and 9 have the same address and the data is "1", it is possible to proceed to the next address from that address and to other than the next address. This means that both of the actions of jumping are performed. When this result is instructed by the read instruction signal 112, the read control circuit 6 switches the select signal 601 to the address 602 side and sequentially increments the read data 701, 801, 901 to the storage circuits 7, 8 and 9.
The data inside will be read.

FIG. 2 shows another circuit configuration which can obtain the same result as the above.

In FIG. 2, the instruction storage circuit 2 is previously stored.
Check the address of the jump instruction in 0,
As the jump destination of the address, the next address is stored in the storage circuit 150, and the jump destination which is not the next address is stored in the storage circuit 160. Therefore, when the address instruction output from the address 401 is a jump instruction, the next address is output from the read data 151 of the storage circuit 150, and a jump address other than the next address is output from the read data 161 of the storage circuit 160. become.

By comparing the read data 151 and 161 with the instruction address 301 and the comparators 130 and 140, either of the output signals 131 and 141 on the matched side becomes "1", and the data is stored in the storage circuit 8.
Written to 0 and 90.

The data written in the memory circuits 70, 80 and 90 will be the same as the result described with reference to FIG.

As described above, the history can be known not only for the history that the instruction of the address was simply executed as the address executed by the processor 10 but also for the branch of the jump instruction.

[0021]

By adopting the configuration as described above, according to the present invention, it becomes possible to leave a history of the branch of the conditional JUMP instruction as the operation of the firmware during the debugging of the firmware, thereby increasing the coverage rate of the operation. There is an effect that becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the present invention.

FIG. 3 is a diagram showing an example of an instruction group for explaining the operation of the present invention.

FIG. 4 is a diagram showing an order of executing the instruction group of FIG.

5 is a time chart of the instruction execution shown in FIG.

FIG. 6 is a diagram showing stored contents of a storage circuit as a result of the operation shown in FIG.

[Explanation of symbols]

1, 10 processor 2, 20 instruction storage circuit 3, 4, 30, 40 address register 5 arithmetic circuit 6, 60 read control circuit 7, 8, 9, 70, 80, 90, 150, 160 storage circuit 11, 110 instruction control Circuit 12,120 Selector 130,140 Comparator

Claims (2)

[Claims] 1. An instruction storage circuit for storing an instruction executed by a processor, a first address register for storing an address executed by the processor, and one instruction before the instruction indicated by the first address register. A second address register for storing the executed address, an arithmetic circuit for arithmetically operating the output data of the second address register and the first address register, and 3-bit input / output with the same address capacity as the instruction storage circuit. A first memory circuit having a data width, and an instruction control circuit for giving a memory instruction to the first memory circuit according to an instruction from a processor, and the second memory is provided on an address line of the first memory circuit. Output data of the address register is connected, and a 1-bit signal of logic "1" and the operation are connected to the 3-bit input data line of the first memory circuit. And an execution clock supplied to the processor is a write signal for the first address register, the second address register, and the first memory circuit. A firmware execution history storage method characterized by being connected to. 2. A second memory circuit which does not have the arithmetic circuit and which stores in advance address data obtained by adding 1 to the address where the conditional jump instruction in the instruction storage circuit is stored, and the same instruction. No. 3 that stores the jump destination address data of
Storage circuit, the output of the second address register is connected to the addresses of the second storage circuit and the third storage circuit, and the instruction of the address data of the second address register is a conditional jump instruction. In this case, the address obtained by adding 1 to the address of the instruction is output from the second storage circuit as the shamp destination address, and the third storage circuit outputs the second storage circuit and the third storage circuit. 2. The firmware execution history storage system according to claim 1, wherein the output of the first address register is individually input to a comparator, and the result of the comparison is connected to the input data of the first storage circuit as a coincidence signal. ..