JPH0623952B2 - Micro program controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a micro program control device in an information processing device having an arithmetic processing device which is micro program controlled.

<Prior Art> Generally, in an information processing device that requires high performance,
While a storage device is hierarchized by a cache memory in order to speed up the reading of data from the main storage device, a pipeline type arithmetic processing device is used for speeding up the arithmetic processing.

In the former cache memory, a copy of the data that is used frequently in the main memory is stored in a small-capacity, high-speed memory, and the data in the main memory necessary for the calculation exists in the cache memory. When this is done, it is possible to fetch this at high speed, but if the required data is not on the cache memory, it must be fetched directly from the low-speed main memory, and at this time, this data is used as operand data. The processing of the required arithmetic instruction cannot be started until the data is fetched.

The latter pipeline type arithmetic processing unit divides an arithmetic processing process for one instruction into a plurality of arithmetic stages,
Each time an operation stage of an instruction in the arithmetic processing unit advances, new instructions are sequentially supplied to the empty arithmetic stage to speed up the arithmetic processing. When an instruction refers to the operation result of an instruction currently being processed in the arithmetic processing unit as operand data, the processing of the next instruction cannot be started until the processing of the instruction being processed is completed.

As described above, in a cache memory or a pipeline type arithmetic processing device used as a method for increasing the speed of an information processing device, operand data required for instruction processing is not always obtained in a fixed time, and in general, Whether or not an event of waiting for these operand data occurs cannot be known until immediately before the start of the processing of the instruction.

FIG. 1 is a block diagram showing an example of a conventional information processing apparatus having a microprogram-controlled groove calculation processing apparatus. Control memory device 1 storing microinstructions of multiple words
The microinstruction a fetched from 0 is first held in the microinstruction register 20. The microinstruction (b) held in the microinstruction register 20 controls the arithmetic processing circuit 40 and is sent to the operand data supply unit 30 to instruct the arithmetic processing circuit 40 to supply the operand data. The operand data supply unit 30 includes an arithmetic processing circuit 40.
If the operand data can be supplied without delay, the operand data (d) is supplied as it is, but if there is a wait for the operand data, this effect c is sent to the control storage device 10,
The micro instruction register 20 is notified, and the execution of the instruction and the subsequent instruction group is waited until the operand data d can be supplied to the arithmetic processing circuit 40.

FIG. 2 shows the time chart at this time. The operand data waiting occurs due to the microinstruction A, and the operand data supply unit 30 notifies the control memory device 10 and the microinstruction register 20 of that fact. Then, in the machine cycle 3 after the lapse of 2 machine cycles, the operand data d is supplied to the arithmetic processing circuit 40. That is, waiting for two machine cycles has occurred for the supply of the operand data d. In the machine cycle 4 in which the supply of the operand data d is completed, the instructions B and C following the microinstruction A are sequentially supplied to the operand data supply unit 30 and the arithmetic processing circuit 40 and executed.

As described above, in the information processing apparatus of FIG. 1, the operand data supply unit 30 which receives the micro instruction from the micro instruction register 20 determines whether or not the operand data d can be supplied, and as a result, cannot supply. If it is determined that the update of the control memory device 10 and the micro instruction register 20 is to be suppressed, these processes must be completed within one machine cycle.
Therefore, in order to reduce the time per machine cycle to increase the speed of the information processing device, the micro instruction restorer 20
To the control storage device 1 via the operand data supply unit 30
Due to the delay time of 0 and the transmission of information to the micro instruction register 20, the update of the micro instruction register 20 cannot be suppressed, and further speeding up is impossible.

<Object of the Invention> Therefore, it is an object of the present invention to provide a microprogram controller which shortens the time per machine cycle of an information processing apparatus to increase the speed.

<Structure of Invention> A microprogram control device of the present invention includes a control storage device for storing a plurality of microinstructions for controlling an arithmetic processing device, and a storage unit for holding the microinstructions read from the control storage device. Selecting means for selecting one of the first microinstruction read out from the control storage device or the second microinstruction held in the storage means as an execution microinstruction and supplying it to the arithmetic processing unit. And a means for detecting that the execution microinstruction is normally executed in the arithmetic processing unit, and the detecting means when the execution microinstruction supplied to the arithmetic processing unit is not normally executed. In response to, the selecting means operates to select the second microinstruction as an execution microinstruction, and the storage means operates. To keep the second microinstruction with the current contents of

<Example> Hereinafter, an example of the present invention will be described with reference to the drawings.
FIG. 3 is a block diagram of an information processing apparatus equipped with a micro program controller according to an embodiment of the present invention.

The micro program controller of the present embodiment is an arithmetic processing unit (arithmetic processing circuit 40, operand data supply unit 30).
Control memory device 10 'for storing a plurality of microinstructions for controlling the memory, a microinstruction register 21 for holding a microinstruction of one word fetched from the control memory device 10', and a microinstruction register 21. The micro-instruction that was stored in the micro-instruction register 21 immediately before the current micro-instruction stored in the micro-instruction register 21.
The microinstruction buffer register 22 for holding the microinstruction fetched from 0 ', and one of the microinstruction in the microinstruction register 21 and the microinstruction in the microinstruction buffer register 22 are selected as the execution instruction microinstruction, and To the arithmetic processing circuit 40 and the operand data supply unit 30
And the operand data wait signal from the operand data supply unit 30 cannot control the control storage device 10, the micro instruction register 21, and the micro instruction buffer register 22 within one machine cycle, and thus can be held within one machine cycle. It comprises a wait control register 60.

FIG. 4 is a time chart showing an operation example of this embodiment. The microinstruction A fetched from the control memory device 10 'in the machine cycle 0 is held in the microinstruction register 21 in the machine cycle 1 and the next microinstruction B is fetched from the control memory device 10'. At this time, no waiting for operand data has occurred in the machine cycle 0. Therefore, in the machine cycle 1, the operand waiting signal C ₁ is sent to the wait control register 60.
Is not retained. So microinstruction selector 50
Selects the microinstruction register 21 and supplies the microinstruction A as the execution microinstruction b to the arithmetic processing circuit 40 and the operand data supply unit 30. The operand data supply unit 30 decodes the microinstruction A supplied from the microinstruction selector 50, knows that the operand data d should be supplied to the arithmetic processing circuit 40, and at the same time, the waiting of the operand data occurs. When this is detected, the signal C ₀ is sent to the wait control register 60.

In the present invention, the operand data waiting signal C ₀ is
It need only be generated at such a timing that it can be stored in the wait control register 60, and it is not required to further suppress the update of the micro instruction register 21 and the like within the same cycle as in the conventional technique. In machine cycle 2, the microinstruction B fetched from the control storage device 10 'is held in the microinstruction register 21 and the next microinstruction C is stored.
Are retrieved from the control storage device 10 '. On the other hand, the microinstruction A which has not been executed by the arithmetic processing circuit 40 for waiting for operand data in the machine cycle 1 moves from the microinstruction register 21 to the microinstruction buffer register 22 in the machine cycle 2. At this time, since the wait control register 60 holds the wait signal C ₁ of the operand data generated in the machine cycle 1, the microinstruction selector 50 switches to the microinstruction buffer register 22 and the microinstruction register 21 and The microinstruction buffer register 22 continues to hold the current contents without changing to a new microinstruction, and the arithmetic processing circuit 4
The microinstruction A which has not been executed in the machine cycle 1 is continuously supplied to the 0 and the operand data supply unit 30. Therefore, the microinstruction A held in the microinstruction register 21 in which a wait for operand data occurs
The execution of the wait signal issued in the machine cycle 2 after 1T because the update of the control storage device 10 and the micro instruction register 21 cannot be suppressed by the wait signal C ₀ generated in the machine cycle 1 due to the faster machine time. It is controlled by C ₁ to hold the microinstruction A set in the microinstruction buffer register 22 together with the microinstruction register 21 until the operand data is determined. As a result, the microinstruction selector 50 is provided with the waiting signal C _{1 while} being issued.
The output of the micro instruction buffer register 22 is continuously selected. When the waiting of the operand data detected in the machine cycle 1 is canceled in the machine cycle 3 and the operand data d is supplied to the arithmetic processing circuit 40, the microinstruction A is executed in the machine cycle 3. However, the wait control register 60 still holds the operand data waiting signal C ₁ , and the control storage device 10 ′, the micro instruction register 21, and the micro instruction buffer register 22 are used in the machine cycle 4 and the previous machine. It remains the content of the cycle. on the other hand,
The microinstruction selector 50 selects the microinstruction register 21 and outputs the microinstruction B because the contents of the wait control register 60 in the machine cycle 4 do not instruct to wait for operand data. In the machine cycle 4, as in the case of the machine cycle 1, since the operand waiting signal C ₁ is not held in the wait control register 60, the micro instruction selector 50 selects the output b ₀ of the micro instruction register 21 to select the micro instruction. Output B. As a result, the microinstruction B is executed in this machine cycle 4. Further, since the operand wait signal C ₁ is released, the control storage device 1 is not activated when switching to the next machine cycle 5.
0, the outputs of the micro instruction register 21 and the micro instruction buffer register 22 change.

In the machine cycle 5, since the wait control register 60 does not hold the operand wait signal C ₁ as in the previous machine cycle, the microinstruction selector 50 selects the output b ₀ of the microinstruction register 21 and outputs the microinstruction C. To do. As a result, the micro instruction C is executed in this machine cycle 5. Further, since the operand wait signal C ₁ is released, the control storage device 1 is not activated when switching to the next machine cycle 5.
0, the outputs of the micro instruction register 21 and the micro instruction buffer register 22 change.

In the machine cycle 6 as well, as in the previous machine cycle, since the operand wait signal C ₁ is not held in the wait control register 60, the microinstruction selector 50 selects the output b ₀ of the microinstruction register 21 and outputs the microinstruction D. To do. As a result, the micro instruction D is executed in this machine cycle 6. Further, since the operand waiting signal C ₁ is released, the control storage device 10, when switching to the next machine cycle 7,
The outputs of the micro instruction register 21 and the micro instruction buffer register 22 change.

From the above description, the microinstruction A, which is supposed to be executed in the machine cycle 1, has been extended until the machine cycle 2 which is two machine cycles later due to the waiting of the operand data in the machine cycles 1 and 2. It is also understood that the execution of the subsequent microinstructions including the microinstruction B is automatically extended accordingly.

<Effects of the Invention> As described above, according to the present invention, a buffer memory is provided in the microinstruction storage means and the microinstruction storage means is switched to the buffer memory after operand data waiting occurs. , It becomes unnecessary to immediately suppress the update of the micro instruction register etc. during the machine cycle in which the waiting of the operand occurs.
It is possible to prevent the delay time of the micro program control device from hindering the speeding up of the information processing device.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus having a conventional micro program control device, FIG. 2 is a time chart showing an example of its operation, and FIG. 3 is a micro program control device according to an embodiment of the present invention. A block diagram of the information processing apparatus and FIG. 4 are time charts showing an example of its operation. 10 ': control storage device, 21: micro instruction register,
22: Micro instruction buffer register, 30: Operand data supply unit, 40: Arithmetic processing circuit,
50: Microinstruction selector, 60: Wait control register.

Claims (1)

[Claims] 1. An information processing apparatus having an arithmetic processing unit controlled by a micro program, comprising: a control storage unit for storing a plurality of micro instructions for controlling the arithmetic processing unit; and a micro processor read from the control storage unit. Storage means for holding an instruction; operand data supply means for supplying operand data to the arithmetic processing unit; first microinstruction currently read from the control storage device or the storage unit currently read from the control storage device; Selection means for selecting one of the second microinstructions held in the means as an execution microinstruction and supplying it to the arithmetic processing unit and the operand data supply means; Detecting means for detecting When the occurrence of waiting is detected, the selecting means operates to select the second microinstruction as an execution microinstruction, and the storage means keeps holding the second microinstruction having its current content. A microprogram controller characterized in that it operates.