JPS61237136A - Register controlling system - Google Patents

Abstract

PURPOSE:To quicken a start of execution of a branch destination instruction by executing a control so that a precedence store is inhibited even if execution of an index register store instruction is started, when a conditional instruction displaying circuit is in a set state. CONSTITUTION:A decoder 10 decodes an instruction code, and supplies a result of this decoding to the first control circuit 11. Then, in case a condition branch instruction TZE precedes index register store instructions EAX 1, EAX 2, a conditional instruction displaying circuit in the circuit 11 becomes a set state between timings t1-t3, therefore, the circuit 11 stops outputting a control signal for instructing write to the second index register group 4. When a precedence store to the register group 4 is inhibited in this way, even if the instruction TZE is executed in an executing state E and made to branch to a load instruction LDA, it will suffice by only cancelling a result being on the way of execution of the instructions EXA 1, EXA 2, LDA, etc. which follow the instruction TZE, by a write stage W of the instruction TZE, and a release of registers X1, X2 becomes unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a register control method, and particularly to a register control method in a data processing device employing a pipeline method. More specifically, the present invention relates to a register control method that improves conflict avoidance between writing and reading to registers.

(Prior Art) As is well known, the pipeline method is a high-speed calculation method suitable for vector processors dedicated to processing such as calculations on large vectors and matrices. The concept is that input data (in a broad sense) is input one after another at a fixed machine cycle into a pipeline consisting of multiple stages, and the processing corresponding to each stage is performed at each machine cycle to proceed with the calculation. An operation on input data is completed by passing through all stages. We aim to speed up calculations based on the principle that if the input data string is long enough, calculations that would otherwise take time equal to the machine cycle time multiplied by the number of stages can be obtained every machine cycle time. There is.

The reason why the pipeline method is established is based on the premise that each piece of input data can be independently calculated. However, before the execution of the instruction to store in the register is completed,
An instruction to read the register may follow as input data. In the pipeline arithmetic system, such a case occurs in the index register used for address calculation. That is, there is a case where an instruction to read the index register and use it for address calculation follows before the instruction to store the instruction execution result in the index register is completed.

Conventionally, in such a case, the subsequent instruction is allowed to start its execution until the register store instruction is completed.

However, this naturally reduces performance, so an index register for address calculation is provided, and in the case of an instruction whose instruction execution result can be obtained in the previous stage, this instruction execution result is used as an index register for address calculation. A register control method has been proposed in which the waiting time for address calculation is shortened by storing the information in advance in a register and using it for calculating the address of a subsequent instruction.

(Problems to be Solved by the Invention) In such conventional methods, advance storage to the index register is carried out on the premise that it is effective in the flow of processing. On the other hand, if a conditional branch instruction precedes the execution of the conditional branch instruction and the flow of υ processing must be branched depending on the result of execution of this conditional branch instruction, in addition to canceling the execution of each instruction in the middle of execution following the conditional branch instruction, Since it is necessary to restore the index register that has been previously stored, there is a problem in that the start of execution of the branch destination instruction is delayed by that time.

FIG. 3 is a time chart that clearly shows this problem. Next to the conditional branch instruction TZE, two index register storage instructions EAXI and EAX2 and a load instruction LDA are shown.
This is the case where a store instruction STA follows. The pipeline consists of a decoding stage D, an address generation stage,
From address translation stage P, cache access stage C1, execution stage E and write stage W,
By passing through each of these stages in this order, execution of one instruction is completed.

In each address generation stage of index register storage instructions EAX1 and EAX2, advance storage to specified index registers X1 and X2 occurs at timing t, respectively.
, is executed at t3, but as a result of the conditional branch instruction TZE reaching the execution stage (timing t4~'s) and being executed, if a condition such as branching to address's load instruction LDAK is established, execution is executed by timing t. All instructions started, ie addresses A, , A2 . A3 and Mr.'s index register storage instruction EAX1. Index register storage instruction BA, X2. The load instruction LDA is canceled during the execution of the store instruction 8TA at timing t, ~t6, and the timing t, ~t
At timings 6 and t and up to t, index registers X1 and X2 must be restored, that is, returned to the state before the preceding storage. As a result, execution of the branch destination load instruction LDA does not start until timing t7 when the above-described cancellation and restoration are completed.

An object of the present invention is to provide an index register control method that eliminates the delay in the execution start time of a conditional branch instruction by the index register recovery time in the conventional method.

(Means for Solving the Problems) The method of the present invention comprises: an instruction register that holds instructions in the decoding stage of a pipeline; a first register group that holds execution results executed by the pipeline; and an execution result. a second register group that holds as an index value for address calculation; an adder that adds the specified value held in the second register group and the displacement address of the instruction when instructing index modification of the instruction; Selectively accept the output or execution result of the second
A switch that supplies write data to a group of registers, and a conditional branch instruction that maintains the set state only from the address generation stage to the instruction execution stage when the decoding result of the instruction in the instruction register is found to be a conditional branch instruction. When an instruction to load the adder output into the runster group and the second register group is input to the instruction register, the switch accepts the output of the adder and the conditional branch instruction display circuit is in the reset state. If there is, the output of the adder is supplied as write data to the second register group and loaded in advance into the first register group, but when the conditional branch instruction display circuit is in the set state, the advance loading operation is suppressed. It is characterized by

(Function) The present invention suppresses the preceding storage in the index register when an instruction that instructs to store the adder output in the index register follows before the execution stage of the conditional branch instruction. However, the reason why such a measure would result in the loss of the opportunity to improve performance through advance address calculation is that the execution of the conditional branch instruction would not result in a branch, and the conditional branch instruction would not be executed following the index register storage instruction. This is only possible if there are consecutive instructions that instruct to read the same index register up to the stage.

It is K to branch depending on the result of execution of a conditional branch instruction,
This method is based on the fact that the situation is extremely rare compared to the conventional method in which it is necessary to restore the previously stored index register.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, in this embodiment, instruction register 1. Switcher 2. Pace register group 3. Second index register group 4. Address adder 5. Effective address adder 6. Address conversion circuit 7. Cache memory8. Effective address stack9. Decoder 10. First control circuit 11. A command control unit consisting of a control stack 12 and two switchers 13
and 14, two working registers 15 and 16
．． Arithmetic unit 17. The instruction execution unit includes a first index register group 18 and a second control circuit 19.

Instruction register 1 holds the instruction immediately after input to the pipeline, this instruction code OP is stored in decoder 10, and pace address registers I and B are stored in pace register group 3. The index register number X is the second index register group 4.
The displacement address Y is then supplied to an address adder 5 and an effective address adder 6.

The decoder 10 decodes the instruction code OP and supplies the decoding result to the first control circuit 11 and the control stack 12.

The first control circuit 11 includes a conditional branch instruction display circuit (not shown) that is set in a set state only until the execution stage E when the decoding result is a conditional branch instruction. The base register group 3 is accessed with the base address register number B, and the second index register group 4 is accessed with the index register number X.
The base address from is read out to address adder 5, and the index address from second index register 4 is read out to address adder 5 and effective address adder 6, respectively. The above decoding of the instruction code and reading of the base address and index address are the decoding stage D of the pipeline.

In response to a control signal from the first control circuit 11, the address adder 5 adds a base address from the base register group 3, an index address from the second index register group 4, and a displacement address from the instruction register 1. The effective address adder 6 adds the index address from the second index register group 4 and the displacement address from the instruction register 1 in response to a control signal from the first control circuit 11. is added to generate an effective address (address generation stage A).

The virtual address is converted into a real address by the address displacement circuit 7 (address conversion stage P), and the cache memory 8 is accessed using this real address (cache access stage C). Various control signals necessary for address translation and cache memory access are supplied from the first control circuit 11.

During this time, one effective address is stack-stored in the effective address stack 9 and is supplied to the switch 2.
accepts either an instruction execution result or an effective address, which will be described later, in response to a control signal from the first control circuit 11.

The control stack 12 stores instructions that have been decoded and are yet to be executed in the decoder IOK, and in the Yayashe access stage C, the read data from the cache memory 8 and the effective address from the effective address stack 9 are switched. The decoding results of the instructions corresponding to these addresses are sent to the second address 13 and 14 simultaneously.
The signal is supplied to the control circuit 19.

In the effective stage E, each of the switches 13 and 14 responds to a control signal from the second control circuit 19 to switch between the cache memory read data and the effective address stack 9.
Effective address from and first index register group 18
It accepts either read data or "O#" and supplies them to working registers 15 and 16, respectively.

The access address for the first index register group 18 at this time is given from the second control circuit 19.

The arithmetic unit 17 performs arithmetic operations on the contents held in the working registers 15 and 16 in response to the control signal from the second control circuit 19, and transfers the instruction execution results to the switch 2 and the first index register group 18. The data is supplied to the cache memory 8.

In the write stage W, the switch 2 is connected to the first control circuit 1
1, the first index register group 18, and the cache memory 8 accept the instruction execution results in response to control signals from the second control circuit 19, respectively.

By passing through the above-described decoding stage D, address generation stage, address translation stage P, cache access stage C1, execution stage E, and write stage W in this order, the execution of the first instruction is completed.

Now, as described above, the switchers 13 and 14 accept various inputs corresponding to the instruction code OP, and supply them to the arithmetic unit 17 via the working registers 15 and 16. The arithmetic unit performs an operation corresponding to the instruction code OF on this input to obtain an instruction execution result, which is supplied to the switch 2, the cache memory 8, and the first index register group 18 in the execution stage E. And in the case of many commands,
In the write stage W, the data is written to the cache memory 8 or the first index register group 8 and the second index register group 4.

By the way, there is an index register storage instruction that instructs all the effective addresses obtained by the effective address adder 6 to be stored in the index register.

As is well known, it is often used during vector calculations.

In the index register storage instruction, the switch 2 accepts the effective address obtained by the effective address adder 6 and tries to write it to the second index register group 4 in the address generation stage A.

In addition, the switching devices 13 and 14 are connected to the above-mentioned effective address and "0".
is accepted by the cache-access stage C, and the calculation unit 1
7 (in this case, the addition is meaningless), the write stage W attempts to write to the first index register group.・In other words, since the instruction execution result may have already been obtained at address generation stage A, the pipeline can be improved by pre-storing this at address generation stage A and using it for calculating the address of the subsequent instruction. They are trying to achieve the same effect as shortening the length. Such advance storage may be allowed only as long as it is determined that other instructions preceding the index register store instruction are valid based on the results of execution in the effective stage E.

Therefore, as shown in the time chart in Figure 2, K
, when the conditional branch instruction TZB precedes the two index register storage instructions EAX1 and FliAX2, as described above, the conditional instruction display circuit in the first control circuit 11 displays the information between timing t and timing t5. Since the first control circuit 11 is in the set state, the first control circuit 11 stops outputting the control signal instructing writing to the second index register group 4. As a result, when the conditional instruction display circuit is in the reset state, timing t, timing t,
Preliminary storage to index register X1 and index register X2, respectively, is inhibited.

By inhibiting advance storage to the second index register group in this way, conditional branch instruction TZR can be executed at execution stage E.
Four instructions EAXI following the conditional branch instruction TZH result in a branch to the load instruction LDA at address b.

EAX2. It is only necessary to cancel the execution results of each instruction LDA and 8TA in the write stage W of the conditional branch instruction TZE, and as before, the index register
1 and X2 are not required, execution of the branch destination instruction LDA can be started at timing t.

However, as a result of executing the conditional branch instruction TZE at execution stage E, the branch does not occur and the address →A, →A, →A, →A
4..., if there is an instruction to read index register X1 at address kst or A4, or if there is an instruction to read index register X2 at address A4. If there are such instructions, the start of these instructions will be 3 to 2
This will cause a delay by the amount of machine time. However, in such a critical case, there is no need to take multiple branches as a result of executing a conditional branch instruction, and it is necessary to restore the previously stored index register as in the conventional method. Because it is extremely rare compared to
The probability of losing an opportunity to improve performance through advance address calculation is extremely low, and a significant overall performance improvement is expected.

(Effects of the Invention) According to the present invention, as explained above, in the case of a conditional branch instruction, a conditional instruction display circuit is provided that is set only from the decoding stage to the execution stage, and this circuit Even if the index register storage instruction starts executing when the conditional branch instruction is executed, the preceding storage to the index register is suppressed. Since the restoration of the index register, which was necessary due to the preceding storage in the index register, is no longer necessary, the start of execution of the branch destination instruction can be started earlier.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, FIG. 2 is a diagram for explaining this embodiment, and FIG. 3 is a diagram for explaining a conventional example. 1...Instruction register, 2.13.14...°°
...Switcher 13...Pace register group, 4...
...Second index register group, 5...
Address adder, 6... Effective address adder,
7... Address conversion circuit, 8... Cache memory, 9... Effective address stack,
10...decoder, 11...-first control circuit, 12...control stack, 15.16...
...°゛Working register, 17... Arithmetic unit, 18... First index register group, 19
...Second ititi control circuit. Certain /I! 1

Claims (1)

[Scope of Claims] An instruction register that holds instructions in the decoding stage of a pipeline, a first register group that holds execution results executed by the pipeline, and holds the execution results as an index value for address calculation. an adder that adds the specified holding value of the second register group and the displacement address of the instruction when the instruction instructs index modification; and an output of the adder or the displacement address of the instruction. a switch that selectively accepts an execution result and supplies it as write data to the second register group; and when it is determined that the result of decoding the instruction in the instruction register is a conditional branch instruction, the instruction is transferred from the address generation stage for the instruction. a conditional branch instruction display circuit that maintains a set state only until the execution stage, and when an instruction to load the output of the adder into the first register group and the second register group is input to the instruction register, the switch accepts the output of the adder and supplies the output of the adder as write data to the second register group and loads it in advance to the first register group if the preconditional branch instruction display circuit is in a reset state. A register control system characterized in that when the conditional branch instruction display circuit is in the set state, the preceding load operation is suppressed.