JPH01305452A - Store control system for buffer memory device - Google Patents

Abstract

PURPOSE:To prevent a successive instruction from being delayed due to the write operation of a pipeline by performing a write operation on a buffer memory device by utilizing the free time of a data part in the buffer memory device. CONSTITUTION:Data read out from a tag part 2 is compared with the low-order address of an effective address register 1 at a comparison part 13 in a store operation, and when they coincide, those are stored in an address buffer circuit 4, and store data is stored in a data buffer circuit 5. Read sequence precedes at the time of applying Popfch based on a fetch instruction, and a block address is inputted to the tag part 2 and the data part 3, and write sequence is supplied from the address buffer circuit 4 to the data part, and the store data to a data register 15 delaying by one cycle. In such a way, it is possible to prevent the following instruction from being delayed due to the write operation of the pipeline.

Description

[Detailed Description of the Invention] [Summary] Regarding a store control method for a buffer storage device in a data processing device equipped with a buffer storage device including a tag section and a data section, read operations and write operations to the buffer storage device overlap. The purpose of this method is to provide a store control method for a buffer storage device that does not cause a read delay even in the case of a buffer storage device. In a data processing device that has a buffer storage device, a store address for store access to the main storage device, and a store buffer mechanism that temporarily holds store data, when fetching data from the buffer storage device, a tag section and a store address for store access to the main storage device are used. When processing is performed using a read sequence that uses the data section at the same time and data is stored in the buffer storage device, there is a check sequence that uses only the tag section to check whether there is an address block to be stored, and an actual Processing is performed using a write sequence that writes to the data section, and in the check sequence, the store address and store data are simultaneously stored in the store buffer mechanism, and the store write sequence is as follows:
The access priority to the buffer storage device is set lower than that of the read sequence, and after the subsequent read sequence is processed first, the store data and store address are restored from the store buffer mechanism and the write sequence is processed. do.

[Industrial Field of Application] The present invention relates to a store control method for a buffer storage device in a data processing device equipped with a buffer device including a tag section and a data section.

In recent years, in order to speed up main memory access time, many devices have adopted a two-layer memory system consisting of a buffer storage device and a main storage device. The buffer storage device is typically a tag section (TA
G: Directory section) and data section (DATA)
When data is stored in the data part of the tag part, a part of the address (block address) of that data is held in the corresponding tag position.

Each is composed of multiple ways.

In addition, each tag section and data section consists of multiple blocks that are units of storage or transfer, and the tag section indicates the validity of the block (data transferred from the main memory) corresponding to each block. It has a valid bit indicating that it has been read and written (meaning it is read and written).

In data processing that has a memory system consisting of two layers, a main memory device and a buffer memory device, when accessing the memory, first check if there is data at the address corresponding to 8 in the buffer memory device, and check if the above-mentioned tag When searching for each way in the section, look at the address -ff and I, and if no match is found for the address from any way, it means that the desired data does not exist in the buffer storage device. Generally, the data at the address is read from the main memory and transferred to the buffer storage device, and thereafter the data at that address is controlled so as to perform memory access to the buffer storage device.

Furthermore, in the store-through type buffer store control method, when performing a store access to the main memory WW, if the address block for the store access exists in the buffer storage tα device, the store access is also made to the buffer storage device at the same time. If the buffer storage device does not exist, store access is not performed to the buffer storage device, and store access is performed only to the main storage device.

When a data processing device that performs pipeline processing performs a store access to such a buffer storage device, the fetch operation by a subsequent instruction or the check operation before the store access overlaps with the above store operation, resulting in Since fetch operations for subsequent instructions and check operations before store accesses are forced to wait, resulting in loss cycles and reducing the processing capacity of the entire system, it has been desired to provide an effective control method.

[Prior Art] A configuration diagram of a conventional example is shown in FIG. 4, and a time chart of a store operation in the conventional example is shown in FIG.

Figure 4 is a block diagram showing the parts related to the store operation for the buffer storage device.
Configurations specific to reading) are omitted.

In FIG. 4, 40 is a B2 register, 41 is an operand address port (indicated by OP A P), 42 is an effective address register (indicated by EAR: effective address register), 43 is a tag section, and 44 is a plurality of comparators ( 45 is an encoder, 46 is a way number register (W
47 is a data section, 48 is a store data register, 49 is a store address register group (indicated by STAR), 50 is a store buffer data group (indicated by STBD), and 51.52 is a selection circuit.

The buffer storage devices are numbered 43 (tag part) to 4 in Figure 4.
7 (data section) and related circuits. In a store operation from a data processing device equipped with this buffer storage device to the buffer storage device, first, it is checked whether the address to be terminated exists on the buffer storage device, and if there is, the actual write is performed. Take steps.

An effective address register (EAR) 42 receives instruction fetch, operand fetch, and operand store addresses from an instruction unit (not shown) within the data processing device. In a store operation, first, a store address is read from the buffer storage device, and a check is performed to see if the store address is present on the buffer storage device.

At this time, the store address is set in the valid address register 42 of FIG. 4, and the contents of the tag section 43 of the buffer storage device are read out using bits 20 to 25 corresponding to the block address of the buffer storage device. The tag part 43 includes a valid bit (■ bit:
valid) and upper address bit 1 of the block data
~19 are registered.

If the valid bit (V bit) is on, the comparator 44 compares the upper address bits 1-19 with the bits 1-19 of the valid address register 42.

By doing so, it can be determined whether the data at the store address exists in the buffer storage device. If there is a match in the comparator 44, that way number is encoded by the encoder 45, stored in the way number register 46, and used when specifying the way number to be written during an actual write operation.

The store operation time chart shown in FIG. 5 will be explained with reference to the configuration shown in FIG. 4.

First, a priority (indicating the priority order for using the pipeline) Pop fch for sending a store address to the effective address register 42 is set. After this, B1 (buffer 1), B2 (buffer 2)
), the tag section 43 of the buffer storage device is read out, and at the end of the B2 cycle, the way number register 4 is read out.
6 is set. The address of the effective address register 42 is sent to the B2 register 40 in the B2 cycle, and the address of the R
It is stored in the operand address port 41 in cycles.

In the store-through type buffer store control method, it is necessary to also perform store access to the main memory, and the configuration of this conventional example is effective for this purpose.After the address of the address register 42 is set to the B2 register 40 in the B2 cycle, The output is set in the store address register group 49 as shown in FIG. 5 (route 2 in FIG. 4). The store data is then set in a store data register 48 for writing to the data section 47 and a store buffer data group 50 for sending to the main storage device.

When writing to the buffer storage device, Popst (write priority) is set in parallel with the above R cycle (the operand is stored in the operand address port 41), and in cycle St, the write address is stored as the operand. It is set in the effective address register 42 from the address port 41, and in cycles 31 and 82, data is written to the block in the corresponding way of the data section 47 of the buffer storage device specified by the way number register 46.

At this time, the store data from the arithmetic unit (not shown) is sent to the store data register 48 and written to the buffer storage device, and at the same time is set in the store buffer data group 50 as store data to the main storage device.

The store address and store data puffed into the store address register group 49 and the store half-edge data group 50 are sent to the main memory asynchronously with the instruction pipeline through selection circuits 51 and 52 while monitoring the busy state of the main memory. will be sent to.

In the configuration of FIG. 4, although the circuit configuration for reading from the buffer storage tα device such as instruction fetch and operand fetch is not shown, when reading, the tag unit 4
3 and the data section 47 using the block address (pins 20 to 25 of the effective address register), output data from each way of the data section 47 can be obtained.
The output from each way of the tag unit 43 is connected to the pins 1 to 19 from the effective address register 42 and a comparator 44 for each way.
Based on the output from the comparator 44 where a match has been obtained, the output of the corresponding way of the data section 47 is output as read data. In that case, the sequence is Pop fch, B1. in Figure 5. This is done by each cycle of B 2°R.

[Problems to be Solved by the Invention] As described above, according to the conventional configuration, when a store operation occurs, there is only one effective address register 42 for the buffer storage device. There's a problem. This will be explained using a time chart of conventional pipeline processing shown in FIG.

As shown in Figure 6, the store command
After (priority of operand fetch), Bl.

B2. Each cycle of R/Popst, Sl, and S2 is executed in sequence. At this time, if the data processing device sequentially inputs the operand fetch instructions ① to ② by pipeline control, the priorities Pop fch (priority for operand reading) and Popst (priority for storing operand) of ① overlap.

In this case, since the store operation of ■ is given priority, the subsequent instruction, Pop fch of ■, is made to wait and is given priority after the ■ cycle. According to the conventional method, there is a problem in that the processing capacity of the data processing device is reduced due to the occurrence of such a loss cycle.

SUMMARY OF THE INVENTION An object of the present invention is to provide a store control method for a buffer storage device that does not cause a read delay even when a read operation and a write operation to the buffer storage device overlap.

[Means for Solving the Problems] Fig. 1 fa+ shows a store and fetch sequence according to the present invention, and Fig. 1 (bl) shows a basic configuration diagram of a buffer storage device according to the present invention.

In the present invention, the store operation is performed using a check sequence (Pop chk, B1) to check whether the address block to be stored exists in the buffer storage device using the tag section, as shown in A of ta+ in FIG. , B 2゜R)
and a write sequence (Pop st, S 1 , S 2 ) for actually writing to the data section. The fetch operation is shown in B of FIG. 1 (al).

As shown in the following, the read sequence (Pop fch, B 1 , B
2°R). And the buffer description of the write sequence of the store operation! The access priority to the device is set lower than the read sequence.

Figure 1 (in bl, l is the effective address register, 2
is a tag section, 3 is a data section, 4 is an address buffer circuit,
5 represents a data buffer circuit, 6 represents a first selection circuit, 7 represents a second selection circuit, and 8 represents a switching circuit.

In the present invention, a store operation is performed separately into a check sequence and a write sequence, a fetch operation is performed by a busy sequence, and when a write sequence and a busy sequence overlap, a read sequence is given priority, and for this purpose, store data and store data are An address buffer circuit and a data buffer circuit are provided for holding, and output to the data section is controlled by a selection circuit.

[Effect 3 When performing a store operation using a store command, the fat
Execute the check sequence shown in A.

At this time, the tag unit 2 is accessed by the block address of the effective address register 1, and the read data is compared with the lower address of the effective address register 1 in the comparing unit 13. If there is a match, the way number is generated from the encoder 14, and the number information and the address of the effective address register 1 are stored in the address buffer circuit 4.
stored in On the other hand, store data is input from the data processing device at the same time as the address is input, and is stored in one register of the data buffer circuit 5.

When the check sequence of the store operation is completed and the write sequence is subsequently executed, it is checked based on the fetch instruction from the data processing device (Pop fch), and if it is, the write sequence is executed. The sequence is not executed, the fetch operation is started with priority, and the waiting write sequence is executed in the subsequent cycle.In the read sequence, the block address of effective address register 1 is in the tag section. At the same time, the switching circuit 8 is switched to inhibit the output of the first selection circuit 6, and output the block address from the effective address register 1 and input it to the data section 3. The sequence is selected by the selection circuit 6 from the data section hair address circuit 4, outputted, and sent via the switching circuit 8 to the way number (WN
) is supplied to the data section, and at the same time, store data is supplied to the write data register 15 for writing.

Conventionally, if a subsequent store instruction was input into the pipeline when executing a write sequence of a store instruction, the subsequent store instruction could not be executed, but the check sequence by the f&ft store instruction Light sequences can be started at the same time.

[Embodiment] FIG. 2 shows a configuration diagram of an embodiment of the present invention, and FIG. 3 shows a time chart of an operation example of the embodiment.

In Figure 2, 20-25 and 28.29 are the same as 40-45 and 47.48 in Figure 4;
is the B2 register, 21 is the operand address port, 2
2 is a valid address register, 23 is a tag section, 24 is a comparator, 25 is an encoder, 28 is a data section, 29 is a store data register, and 26 is a selector (SEL).
27 is a way number register, 30 is a store address buffer, 31 is a store data buffer, 32 and 33 are selection circuits, and 34 is a comparison circuit (indicated by C).

In this embodiment configuration, the selector 26 is as shown in FIG. 1(b).
The selection circuits 32 and 33 correspond to 6 in Fig. 1 fb).
．． Corresponds to 7. Tag section 23 is valid address register 2
2 bits 20 to 25 are accessed, but the data part 28
For bits 20 to 20 of effective address register 22,
25 as the address or bits 20 to 25 of the store address buffer 30 selected by the selection circuit 32.
You can choose whether to use it as an address. Further, after the way number register 27 holds the output of the encoder 25 in the store address buffer 30, it is selected and set by the selection circuit 32. Furthermore, the buffer storage device does not directly receive store data from an arithmetic unit (not shown);
Once stored in the storage data buffer 31, the selection circuit 3
3, store data register 2 in write sequence
Set to 9.

In the instruction sequence shown in the time chart of FIG. 3, the store instruction (■) uses Pop chk to check whether or not there is data at the address 8 in the tag section 23 of the buffer storage device, and at the same time stores the store address and store data in the main storage device. Data is set in the store address buffer 30 and store data buffer 31. Therefore, the store data to the data section 28 of the buffer storage device is not directly supplied to the store data register 29. This is because if the instruction following instruction (2) is a store instruction again, the subsequent store result cannot be placed on the store data bus unless the store data of instruction (2) is saved.

By buffering the store data buffer 31, the instruction control unit (equipped in a data processing device (not shown)) processes subsequent instructions without waiting for the completion of actual writing to the data section 2 of the buffer storage device. be able to.

The comparison circuit 34 is provided to prohibit a subsequent fetch instruction from using data that has been held in the store address buffer 30 and store data buffer 31 but has not been written to the buffer storage device. The 20 addresses are compared with each of the multiple addresses stored in the store address buffer 30. When a match output is generated by the comparison circuit 34, the output is supplied as a fetch prohibition signal to the instruction control section (not shown).

Since the fetch commands ■ to ■ in FIG. 3 require access to the tag section 23 of the buffer storage device and reading from the data section 28, the selector 26 sets bits 20 to 25 of the effective address register 22 to the data section 2. Send to.

The store instruction (2) sets Popst for the write sequence after the R cycle. In this state, as shown in FIG.
However, in this embodiment, since data is supplied to the store data register 29 via the store data buffer 31, Popst is set with a delay of one machine cycle.

Conventionally, store data is directly input to the buffer storage device, so writing to the data section 28 has to be done H (l first), and Popst has a higher priority than Pop fch, but in this embodiment, store data In order to temporarily buffer Popst in the data buffer 31, the priority of Popst is lowered, so that the i!t'ft instruction is not affected.Therefore, Popst is delayed for one cycle by the fetch instruction (2).

In FIG. 3, when the store instruction is executed again as shown in (3), the check sequence starting with Pop chk accesses only the tag section 23 of the buffer storage device, so the selector 26 moves to the effective address register 22.
Instead, bits 20 to 25 of the store address buffer 30 that have passed through the selection circuit 32 can be used as the access address of the data section 28. Therefore, the write sequence of the store command (2) can be executed simultaneously with the check sequence (2), and the store data is passed through the selection circuit 33, and the contents of the store data buffer 31 are set in the store data register 29. The way number is held in the store address buffer 30.

is passed through the selection circuit 32 and set in the way number register 27.

[Effects of the Invention] According to the present invention, in a data processing device that performs pipeline processing, a write operation to a buffer storage device can be performed using free time in the data section of the buffer storage device. This makes it possible to prevent delays in subsequent instructions due to pipeline write operations, to efficiently execute pipeline processing in the data processing device, and to improve the processing capacity of the entire system.

[Brief explanation of the drawing]

FIG. 1 fa) is a diagram showing a store and fetch sequence according to the present invention, FIG. 1 fh) is a basic configuration diagram of a buffer storage device according to the present invention, FIG. The figure is a time chart diagram of an operation example of the embodiment, Figure 4 is a configuration diagram of a conventional example, Figure 5 is a time chart diagram of a store operation of a conventional example, and Figure 6 is a time chart diagram of pipeline processing of a conventional example. It is. In Figure 1, 1: Valid address register 2: Tag section 3: Data section 4 Near address buffer circuit 5: Data buffer circuit 6: First selection circuit 7: Second selection circuit 8: Switching circuit

Claims (1)

[Claims] A tag unit (2) that holds address information of a buffer storage device.
) and the access mechanism (
1, 4, 6, 8) are independent, and has a store address for store access to the buffer storage device and main storage device, and a store buffer mechanism (4, 5) that temporarily holds store data. In the device, when data is fetched from the buffer storage device, processing is performed using a read sequence that uses the tag section (2) and the data section (3) at the same time, and when data is stored in the buffer storage device, Processing is performed using a check sequence that uses only the tag section to check whether there is an address block to be stored, and a write sequence that actually writes to the data section.In the check sequence, the store address and store data are stored at the same time. Store in the buffer mechanism (4, 5), the store write sequence has a lower access priority to the buffer storage device than the read sequence,
A store control method for a buffer storage device, characterized in that after first processing a subsequent read sequence, the store data and store address are restored from the store buffer mechanism (4, 5) and the write sequence is processed.