JPS5837747A - Instruction read only buffer storage device - Google Patents

Abstract

PURPOSE:To eliminate an instruction buffer and to decrease hardwares, by storing a transfer block from a main storage device and readout data from a data memory to a data buffer in an instruction readout only buffer storage device. CONSTITUTION:In the area assignment in a data buffer 12, a transfer block A from a main storage device 2 is set to the 1st half 4-word, a readout data block B from a data memory 11 is to the latter half 4-word, and bits 27,28 of the address are given to data in each block. Then, an instruction processing section 1 can determine where a desired data is located in the data buffer 12 by managing the distinction of blocks only. The data buffer 12 can be accessed as an instruction buffer for instruction look-ahead, through the address in 3- bit supplied to the data buffer from the section 1, excepting that the desired data is accessed and fetched to the main storage device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer storage device in a data processing device. 41, the buffer storage is divided into two parts, one for instruction read only and one for operand read only.
Regarding K, the instruction read-only buffer storage location O control method 2 E1m.

The buffer memory provided for accessing the main memory of the logic device is used for two purposes: reading instructions from the logic device and reading operands specified by each instruction. 1 per machine cycle for a single buffer storage
In order to execute one operation, the two types of read KFi require two machine cycles, and require 42 machine cycles at the maximum instruction execution speed of a pipelined logic device.

In order to further increase the instruction execution speed and achieve a maximum speed of one machine cycle, K divides the buffer storage lid into two parts, one dedicated to displaying instructions and one dedicated to reading operands. A method is known in which reading for computation and reading of an operand in an instruction to be executed can be performed independently and simultaneously. Conventionally, this type of two-divided buffer storage device can have about half the storage capacity in each of the two divided parts compared to the single buffer storage device, but the memory capacity for data in the address, which is a peripheral circuit of the memory, has been reduced by half. register.

An address comparison circuit, a data selection circuit, a control path, etc. are required for each of the two parts), which has the drawback of greatly increasing the amount of hardware required.

In addition, as a control method when the desired O data does not exist in the buffer storage device, a data buffer is set up to temporarily store data in blocks sent from the main storage device (by accessing the main storage device 4x). However, methods are known to reduce the busy time of buffer storage devices.

According to this method, the block data transferred from the main memory is stored in the -H data buffer 7, and the contents of the data buffer are varied during the free time of the buffer memory O.
By moving data to the data memory of the buffer storage device, it is possible to allow access to the buffer storage device from the logic device even during block transfers.

However, this method also has the disadvantage of increasing the amount of metal.

The present invention improves on this point, making it possible to minimize the increase in the amount of hardware, and further reducing the main memory access time, which conventionally required 02 stages of data buffer and instruction buffer, to 1.
The object of the present invention is to provide a device that can be used for high speed 1 and #& field.

According to the present invention, a data buffer in an instruction read-only buffer storage device and an instruction buffer provided in a 0-instruction processing section in a logic device and temporarily storing a prefetched instruction group have many commonalities in their respective storage contents. The focus is on

The present invention provides that, as the contents of the data buffer in the instruction read-only buffer storage device, in addition to the transfer block from the main storage device described above, a part of the storage contents of the main storage device is further included in the instruction read-only buffer storage device. The data buffer and the instruction buffer are shared by adding read data from a data memory that stores 1g! in blocks. It is characterized by being a buffer of A.

The present invention provides a data memory that stores part of the storage contents of the main memory in block units in an instruction read-only buffer storage, and a data memory that temporarily stores transfer blocks from the main memory and read data from the data memory. When a main memory is accessed from the instruction processing unit, if desired data exists in the data memory, read data from the data memory is written to the data buffer, and when a block transfer from the main memory occurs, The transferred block data is temporarily stored in the data buffer, the valid data block in the data buffer is moved to the data memory during free time, and the data buffer is then used for instruction processing to send its contents to the instruction processing unit. It is characterized by being configured so that it can be accessed directly from the department.

The instruction read-only buffer storage device is logically closely related to the instruction processing section, and the two can be physically located very close to each other. In addition, the block data that is the content of the data buffer is the sequence of instructions to be executed from now on, and by adding successive data from the data memory as the content, it can be used as a prefetching instruction set. .

An embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of main parts of an embodiment of the present invention. Figure 1 shows a public corporation with an instruction processing unit 1, a main storage device 2, and
and an instruction read-only buffer storage device 3. Main memory 2 has a dedicated buffer for operands.
Devices are also connected, but are omitted from this drawing. The buffer storage method in this embodiment has a set number of 64
, a set associative method with a number of connotations of 2 and a block length of 32 bytes is adopted, and block transfer from the main storage device 2 to the buffer storage device 3 dedicated to instruction succession, 1
Although time-division transfer is performed four times by 8 bytes per access, the present invention is not limited to this, and other methods may be adopted.

A part of the memory contents of the instruction read-only buffer storage device 3, the address register 10, and the main memory device 2 are stored in blocks of 32 bytes in length. It also has a data memory 11 of 8 bytes.It also temporarily stores transfer blocks from the main memory 2 (hereinafter referred to as blocks) and successive data from the data memo IJ 11 (hereinafter referred to as blocks B). By using a widely known register file with a configuration of 8 words x 8 bytes,
Corresponding to each block in the data buffer U and data memory 11 that can be read and written at the same time, bits (6
) to (20), a validity bit indicating whether the contents of each block are the same as the contents stored in the main storage device 2, and whether the contents of each block are stored in the data memory 11 or the data memory 13. A management table memory 16 including a management memory 14 for storing a storage position indicating bit indicating which of the buffers exists is provided. Furthermore, each of the outputs for two compartments of the address memory 13 and the address register 100 bits (8) to (20
) and remember the comparison circuit proverb. Also, among the outputs of two compartments of the data memory 11, the comparison circuit 16
A selection circuit 17 is provided for selecting the one for which a match is detected. Furthermore, a selection circuit for selecting the output of either the 1 selection circuit 17 or the main memory device 2 is provided. It also includes a buffer address register east that stores a 6-bit address indicating the storage location in the data memo 911 corresponding to the block among the data in the data buffer n. Furthermore, the 2-bit input address information is set to ``+'' modulo ``4''.
An adder circuit is provided which performs addition of 1 (that is, when the result of addition is 4, sets it to 0) and outputs the result of 2) 0 addition. Furthermore, selection circuits n and B are provided. Furthermore, bit (2) of address register IO
7) , (2a) (B in the figure) and instruction processing unit l
An address generation circuit n which takes as input a 3-bit address (Pm) from , and generates and outputs a write address (Wm) and a subsequent address (Rm) for the data buffer 12.
Equipped with Also, a control circuit U performs communication for controlling access with the instruction processing unit 1 and the main storage device 2, and controls each path in the buffer storage device 3 dedicated for successive instructions.
Equipped with These are arranged and wired as shown in the figure.

In this embodiment, area allocation for type 2 O errors in data buffer n is such that the first 04 words (address value (O) to C5')') of 8 words are used as blocks and the second half 0
4 words (address values (4) to (7)) to plotter BK
II shall be attached.

2nd expansion The address generation circuit shown in Figure 1 ops
FIG. This address generation circuit 2
3, the address register W pin) (27), (
28), only 1 bit is placed above the 2nd bit
A selection circuit Shu and a selection circuit N select a 3-bit address with OJ or a 03-bit address (rm) from the instruction processing unit l and output a translation address (name) to the data buffer 12. Be prepared. It also has an h2-bit write address register whose content is the write address to the data buffer 12 when transferring a block from the main memory 2. Also, the same as addition in the adder circuit〇2
“+1” modulo “4” for the bit input address
Addition circuit that performs addition (and 5-bit address with 1 bit added to the upper part of 2 bits (1 bit) of address register W bits (27) and (28), if there is a mistake, write Select the 3-bit address with one bit added to the upper part of the output O of the address register 3202 (address register 3202 bits), and
A selection a*ttba is provided that outputs Wm). These are arranged and wrapped in 3 #s as shown.

The characteristic operation of the present invention will be explained in this way. In the following explanation of the operation, a case will be described in which, as a result of referring to the validity bit in the management memory 14 at the time of access from the logical device 1, it is found that the desired data is valid, that is, the desired data exists in the data memory 11 or the data buffer.
It is called FB. Conversely, a case where 1 is found to be invalid and the desired data must be accessed to the main memory 2 and fetched is called NFB. In addition, in the operation explanation below,
.

■, ■... - Represents the Hiro machine cycle number, the explanation for each number indicates the operation for one machine cycle, and the value of the number ■, ■, ■... - represents the tying sequence. Top O indicates the order.

(In the case of FB) ■ By referring to the storage position display bit, which is the output of the management memory 140, in the control circuit U, the data memory uPgK
If it is determined that the desired data exists, the data memory 110 read data output is written to the data buffer 12 through the selection circuit 17 and the gate. The write address for this data batzer is a 3-bit address with one bit "1" added to the upper side in the selection circuit 34 for bits (27) and (8)K of the address register 10. Writing to the block power of the latter half 49-word of data buffer L is performed.

(For MOB) Prorate the blocks stored in the data buffer 12K from the previous IO summer νIS. , the block that has become the current MIB is called prolatum 1.

- Generate an access request to the main memory 2 in the primary storage 24 and select one of the 1211 compartments by a replacement algorithm known in the prior art.

Bits (8) to (2.
), and these two bits are stored with polarity such that the validity bit indicates valid and the storage position indication bit indicates the data buffer. OII to the main memory 2 of the prolatum! Information regarding the output, Th, and block A is loaded into the management table memory b.

■ Address register 100 output bits (21) to (
26) to the buffer atris register l, select the buffer address register 190 output, and store it in the address registers 100 bits (21) to (26) via gssin, exchanging the contents of 6 bits each in both registers 10 and 190. and the address register 100 bits (27), (2
8) is stored in the writing column FL/storage register. As a result, the address register 100 bits (21) to (24)
is prolatum. , /(The contents of the Thff address register 19 indicate the address for the prolatum, respectively, and the contents of the write address register 19 indicate the address for the Thff block, KThff.
Indicates the position of the first 8-byte data in the block transfer of the main memory (b).

■ Address register 100 output beep) (27),
(28), in the selection circuit 30, the S bit with 1 bit or OJ added to the upper side is input as the read address, and the 17th address in the data buffer is read, that is, 8/! , the data is read out and stored in the data memory. The storage position of the data memory 11 is read out from the management memory 14 using the outputs (21) to (26) of the address register IO as address inputs, and the storage position display bit indicates the data buffer; Data memory IIK is specified, and bits (21) to (28) of the output of address register W are sent to data memory 110.
This will be the write address.

Prolatum. data buffer 12 to data memo 91
Damage sent to 1, 8 bytes worth.

Furthermore, the output of the address register 10 (p) (j7
), (!8) are added by "+1" in the adder circuit section, and the addition results are stored in the 100-bit address registers (27) and (211) via the selector RalIn.

0 Perform the same operation as above (■).

■ Perform the same operation as ■ above.

■ Performs the same operation as 0 above, and also sets the storage position display bit to prolatum. exists in data memory U ζ
It is stored in the management memory 14 with the polarity indicating ζ (■
After completing the read operation in the main memory device 2 by accessing the main memory device 2 in (2) and waiting for the start of block transfer from the main memory device 2 to the data bazafu, the following O operation is performed. .

■ (n is an integer of 6 or more) 6 bytes of data to be transferred from 2 main memory units to the address location indicated by the S bit, which is the output of the write address register 3202 bits in the data buffer U, with rOJ added to the upper side. Store it in the K.

The output of the write address register is set to ``+1'' in the addition circuit SSS.
J is added, and the addition result is stored in the write address register 32 via the selection circuit 31.

The data is stored in the Blockum and O data buffers.

This amount of data is 8 bytes.

■ When the same operation as above ■ is performed, address register 100 output O bit (27) % (211) The portion 1 has also returned to the value at the time of the access request.

Therefore, as mentioned above, n must be 6 or more (false), the upper K is added to the 2 bits, and 5 bits are added as the read address, and the output of the data buffer 12 is sent to the instruction processing unit l. The instruction processing unit l restarts its operation.

6 King Ri, C) Perform the same action as @. Regarding the value of n mentioned above, since the read operation in the main memory device 2 normally takes W machine cycles, we set n≧6 and change to 1.

Above 1! - As is clearer, the area allocation in the data buffer U is allocated to the first four words of A1, the block 1 to the first four words of A1, and the extended address bits (27) and (28) for the data in each block. Therefore, in the instruction processing unit L, the desired data, that is, the instruction, is stored in the data buffer L at KT.

This can be determined simply by managing the distinction between blocks or blocks B, that is, whether the blocks are based on NνBK or IFBK. The instruction section 3 uses the 3-bit address supplied to the data buffer 12 from the 111 to execute the data buffer 12 as an instruction pre-fetch or instruction passer, except when accessing the main memory at 111FB. Access for reading the instruction is possible.

As explained above, according to the present invention, a transfer block from the main memory is temporarily stored in the data buffer in the instruction read-only buffer storage, and the data buffer contained in the instruction read-only buffer storage is stored in the main memory. It was also decided to store read data from a data memory that stores part of memorized answers in blocks.

Therefore, the data buffer and the instruction buffer can be shared. Therefore, it is possible to eliminate the instruction buffer that was required within the instruction processing section, and the amount of hardware can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an embodiment of the present invention. FIG. 2 is a detailed diagram of the address generation circuit O of the above embodiment. DESCRIPTION OF SYMBOLS 1... Instruction processing unit, 2... Main storage device, 3... Instruction read-only buffer storage device, 10... Address register, 11... Data memory, U... Data buffer, 13... - Address memory, 14... Management memory, 15... Management tape hl memory% 16-jk, Comparison circuit, 17.18.21.22.30.31, Recitation... Selection circuit, 19...・Buffer address register, addition, (・
. . . addition circuit, oh . . . address generation circuit, 24-. control circuit, n . . . write address register. Patent Applicant: NEC Corporation No. 1 Excerpt 2 Figure

Claims (1)

[Claims] (1) Read-only instructions and read-only operands!
In the divided buffer storage device, there is a data memory that stores part of the storage contents of the main storage device in blocks, and a data memory that temporarily stores transfer blocks from the main storage device and read data from the data memory. K11 when accessing the main memory from the instruction processing SS in the logical storage
i. If the desired data exists in the data memory, the read data from this data memory is written into the data buffer, and if the desired data does not exist in the data memory or the data buffer, access to the main memory is performed. The data block transferred due to the occasional access is temporarily stored in the data buffer 7a, and the valid data block in the data buffer is stored using the free time when accessing the new main storage device. is transferred to the data memory. An instruction read-only buffer storage device characterized in that the data buffer is controlled to be accessed directly from the instruction I&R section in order to send the instructions contained in the data buffer to the instruction processing section.