JPH0156411B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a write-swap type cache memory device having a write control method suitable for increasing the speed of continuous data writing when the memory is used as a stack. There are two methods for cache memory devices: a write-through method, in which data is written to both cache memory and main memory at the same time when data is written by the CPU; There are two types of write swap methods that write the previous data to main memory when the same area is later used for cache access at a different address. The present invention belongs to the latter write swap method, and is intended to reduce unnecessary reading of data from main memory to cache memory. [Prior Art] A conventional write-swap type cache memory writing system will be explained with reference to the drawings. FIG. 7 is a configuration diagram of an example of a cache memory device. The address register 30 is a register that holds an address when accessing the cache memory, and consists of three parts: an upper address part 31, a middle address part 32, and a lower address part 33. The data memory 20 is a memory for storing data, and its storage capacity (number of words) is large enough to specify the middle address part 32 and the lower address part 33 by the combined number of bits. data·
The data in the memory 20 is not managed word by word, but is managed in units called blocks, which can be specified by the number of bits in the lower address field 33.
Mishit management and data exchange with main memory are managed. Hereinafter, in this example, the size of one block will be explained as four words. data·
There are as many blocks in the memory 20 as can be specified by the number of bits in the middle address section 32. The directory memory 10 has information such as whether each block in the data memory 20 is valid or invalid, which address the corresponding data is located at, and whether the contents have been changed after being read from main memory to the cache. This information is used to manage whether there is a hit or miss and whether there is a need to transfer data to or from the main memory when reading or writing from the cache memory. The directory memory 10 includes a valid flag section 11, a change flag section 12, and a key address section 13. The number of entries in directory memory 10 is equal to the number of blocks in data memory 20. Comparator 14 compares the value of upper address field 31 in address register 30 with the value of key address field 13, and the result is used to determine whether the cache is a hit or a miss. In this case, directory memory 10 is searched using intermediate address portion 32. The counter 34 has the same bit width as the lower address part 33 (in this example, it is 2 hits), and has zero clear,
It has the function of loading a value from the lower address section 33 and +1, and has the function of sequentially writing the contents (4 words) of the blocks in the data memory 20 to the main memory (writeback) and sequentially writing the contents (4 words) of the blocks in the data memory 20 from the main memory to the blocks in the data memory 20. It is used to generate the lowest (2 bits) address when reading data. The data selector 35 determines whether to use the value of the lower address section 33 or the value of the counter 34 as the lowest (2 bits) of the address supplied to the data memory 20 and main memory. It is assumed that the lower address section 33 is selected. Read data register 21 is a register that holds data to be written to cache memory. The main memory interface 24 is a part that exchanges data, addresses, and control signals with the main memory, and the middle and lower addresses as address information are the same information that is supplied to the data memory 20. , and upper addresses, the contents of the key address part are used in this example. The control circuit 40 starts reading and writing the cache memory according to the cache command placed in the cache command register 41, and reads and writes the directory.
According to the contents of the memory 10, it is determined whether there is a hit or miss, and whether or not data is to be transferred to the main memory, and a control procedure is executed according to the determination results. In FIG. 7, 22 is a read data register, and 23 is a cache data bus. FIG. 8 is a flowchart of the control procedure when write is specified as the cache command. Processing branches depending on the values of the valid flag and change flag in the directory memory 10 and the comparison result of the comparator 14. Branch 1 to branch 4 in the flow diagram
indicates the following cases. Branch 1 is a cache miss when there is no valid data in the block, branch 2 is a cache miss,
Branch 3 is a case where there is valid data in the block, but the key address is different, resulting in a miss, and the contents of the block have not been modified since being brought from main memory (change flag is set). =0) When there is no need to write back to the main memory, branch 4 is a case of a miss similar to branch 3, but the change flag is 1 and the contents of the block need to be written back to the main memory. The control procedure in each case will be explained. In the case of branch 4, since valid data corresponding to valid data corresponding to another address exists in the block in the data memory 20, the contents of the block (4 words) are first written back to the main memory. This process is the 8th
This is the processing in frame 71 in the figure. After the block is emptied in this way, the one word that is about to be written is written in the process of frame 72. Next, the contents of the directory memory 10 are updated in frames 73 and 74. Finally, in box 75, data is read from the appropriate address in the main memory for the remaining three words in the block, and the process ends. The ninth item is the detailed processing of frame 71.
It is a diagram. In order to sequentially read and write the four words of data in the block into the main memory, it is necessary to change the address one by one, and the counter 34 shown in FIG. 7 is used for this purpose. FIG. 10 shows detailed processing of the frame 75. The counter 34 is also used to read data from the main memory for three words in the same block, excluding the address written in box 72 in FIG. The difference with Figure 9 is
First, the lower address part of the address register is loaded as the initial value of the counter, and then it is incremented by 1 and used as the lower address for reading from the main memory. Processing of branches 1 and 3 starts from processing of branch 4 to frame 71.
It is exactly the same as excluding the processing of . Using the conventional cache memory write control procedure described above, when using the memory as a stack and reading (pushing) data from the top of the stack, it becomes clear that Unnecessary main memory reading occurs. This situation will be explained using a diagram. FIG. 11 is a conceptual diagram when memory is used as a stack. In the diagram before writing, the top of the stack is at address 1001 (16), and from now on 1002
(16) An attempt is made to write data to address. ((16) shows hexadecimal display). Dashed lines indicate boundaries of blocks in cache memory. It is also assumed that valid data corresponding to a different address and with a change flag of 1 exists in the cache memory. When writing to address 1002 (16), a miss occurs in the cache memory, and the control procedure of branch 4 in Figure 8 is executed.
First, the original four words of data in the block are written back to main memory, then the data to be written to address 100 (16) is read into the block, directory memory 10 is updated, and the remaining three words in the block are written back to main memory. Words are read from main memory. In the diagram of FIG. 11 after writing, diagonal lines indicate data read from the main memory, and checkered stripes indicate written data. Next, when writing to address 1003 (16),
The cache memory is hit, the control procedure of branch 2 in FIG. 8 is executed, and only the data is written and the change flag is set, and the address 1003 (16) in the diagram after writing in FIG. The diagonal lines change to checkered stripes (Figure 12 before writing). then 1004
(16) When writing to the address, a miss occurs again, and the control procedure of branch 4 in Figure 8 is executed, resulting in 1004 as shown in Figure 12 after writing.
(16) contains write data, 1005 (16) to 1007
At address (16), there is data written from the main memory. The writing process is then repeated, and FIG. 13 shows when writing has been completed for 12 words from addresses 1002 (16) to 100D (16).
Data written from addresses 1002 (16) to 100D (16) exists, and 1000 (16), 1001 (16), 100E
(16), 100F (data automatically read from main memory exists at address (16). In this state, the top of the stack is address 100D (16), and data at larger addresses This data is meaningless to those who use the stack.Also, what should be noted here is that 1002 (16), 1004 (16), 1008
When writing addresses (16) and 100C (16), the cache made a mistake, and 3 words each were read from main memory for a total of 12 words, of which 8 words were 1003 (16). , 1005(16), 1006
(16), 1007 (16), 1009 (16), 100A (16), 100B
(16), the data at address 100D (16) has been overwritten with write data without being used. Furthermore, 100E is unnecessary in terms of stack usage.
(16), 10 words of unnecessary data have been read from main memory, including data at address 100F (16). The following is a summary of hits and misses when writing data to each address mentioned above, the type of cache control procedure activated at that time, and the number of words written to and read from main memory. This is table 1. When 12 words of data are written to the cache memory, 12 words of data are read from the main memory, and 10 of those words are read in vain as described above.

[Problem that the invention seeks to solve]

In the conventional write-swap type cache memory device described above, when the memory is used as a stack, when pushing a series of data of a certain size, data from the main memory that is obviously wasteful is transferred. This is to improve the disadvantage that reading occurs and extra time is required for main memory access. [Means for Solving the Problems] In the present invention, the following measures are taken to solve the above problems. In other words, when writing data, the data is written only in the cache memory, and when the area where the data is written is later used for cache access at another address, the data written in the area is used as the main memory. A write-swap type cache memory that writes data back to memory is provided with a first write means and a second write control means, and when the memory is used as a stack and data is continuously written to the top of the stack, the first The first control means is used to start writing a word, and the second control means is used to start writing the second and subsequent words. If the block does not exist in the cache memory, the write data is written to the data cell at the address after securing the block in the cache memory, and the data for other data cells in the block is read from the main memory. A normal write-swap type control means for reading is implemented, and if the block containing the data cell at the write address does not exist in the cache memory, the second control means replaces the block in the cache memory. Provides a memory control method that immediately writes write data to the data cell at the address after securing the block, and enables the block without reading data from the main memory for other data cells in the block. do. As a result, when the memory is used as a stack in a write-swap type cache memory device, it is possible to reduce the wasted time associated with reading data from the main memory that occurs when writing data to the stack in a continuous manner. It is possible to speed up continuous data writing to the stack. EXAMPLES The present invention will be explained in further detail using Examples below. [Example] An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a cache memory device which is one embodiment of the present invention. In this embodiment, in contrast to an example of the conventional cache memory device explained using FIGS. 7 to 13 and Table 1,
A new cache instruction called write stack is added, and a write stack control circuit 50 and a write stack cache instruction decoder 47 are added to realize the control procedure of this instruction. Control circuit 43, cache instruction decoder 4
6 is equivalent to the control circuit 40 and cache instruction decoder 45 in FIG. 7, and is capable of performing conventional cache instruction control procedures including the cache instruction "write" whose flowchart is shown in FIG. Realize. However, when the cache instruction "Write Stack" is placed in the cache instruction register 41, the cache instruction decoder 46 does not transfer the instruction decoding signal to the control circuit 43, and the control circuit 43 does not transfer the instruction decoding signal to the control signal line 44 and the directory. The signal lines for sending data to the valid flag section 11 and change flag section 12 of the memory 10 are opened, and the control right of the cache memory device is given to the write/stack control circuit 5.
Pass to 0. The write stack cache instruction decoder 47 decodes the write stack instruction,
The command decoding signal is sent to the write stack control circuit 50, and the write stack control circuit 50 sends out a control signal through the control signal line 51, and the write stack control circuit 50 sends out a control signal through the control signal line 51.
Executes the control procedure corresponding to the cache instruction in the stack. The other components in FIG. 1 are the same as those in FIG. The address register 30 is a register that holds addresses when accessing the cache memory, and includes an upper address section 31, a middle address section 32,
The lower address section 33 consists of three parts. The data memory 20 is a memory for storing data, and its storage capacity (number of words) is the middle address part 3.
2. It has a size that can be specified by the combined number of bits of the lower address part 33. data memory 2
The data in 0 is not managed word by word, but
Hits and misses are managed in units called blocks, which can be specified by the number of bits in the lower address field 33, and data exchange with the main memory is managed. Hereinafter, in this example, the size of one block will be explained as four words. data memory 20
There are as many blocks as can be specified by the number of bits in the intermediate address field 32. The directory memory 10 shows whether each block in the data memory 20 is valid or invalid, which address the corresponding data is located at, and whether the contents have been changed after being read from main memory to the cache. It is used to manage whether there is a hit or miss when reading or writing from the cache memory, and whether there is a need to transfer data to or from the main memory. The directory memory 10 includes a valid flag section 11, a change flag section 12, and a key address section 13. The number of entries in the directory memory is equal to the number of blocks in the data memory 20, both addressed by the middle address portion 32 of the address register.
Comparator 14 compares the value of upper address field 31 in address register 30 with the value of key address field 13, and the result is used to determine whether the cache is a hit or a miss. The counter 34 has the same bit width as the lower address section 33 (in this example, it is 2 bits), has the functions of zero clearing, loading a value from the lower address section 33, and +1, and stores the contents of the data memory block (2 bits in this example). It is used to generate the lowest (2 bits) address when sequentially writing data (4 words) to the main memory (write back) and sequentially reading data from the main memory to blocks in the data memory 20. The data selector 35 is
It is determined whether to use the value of the lower address section 33 as the least significant (2 bits) of the address supplied to the data memory 20 and main memory or the value of the counter 34, but usually the lower address section 33 is used. Assume that it is selected. Write data register 21 is a register that holds data to be written to the cache memory. The main memory interface 24 is a part that exchanges data, addresses, and control signals with the main memory, and as address information, the same information as that supplied to the data memory is used for middle and lower addresses.
For the upper addresses, the contents of the key address section 13 are used. FIG. 2 is a flowchart of a control procedure realized by the write stack control circuit of FIG. The flow of the control procedure branches depending on the values of the valid flag section 11 and the change flag section 12 of the directory memory 10 (numbers hereinafter refer to those in FIG. 1 or FIG. 2) and the comparison effect of the comparator 14. In the flow chart, branches 5 to 8 indicate the following cases. Branch 5 indicates that there is no valid data in the block specified by the middle address field 32 of the address register 30, resulting in a cache miss; If valid data exists but the key address comparison result does not match and a miss occurs, and the block contents have not been modified since being brought from main memory (modification flag = 0), write to main memory. If there is no need to restore the block, branch 8 is a case where there is a miss similar to branch 7, but the change flag is 1 and the contents of the block need to be transferred back to the main memory. The control procedure in each case will be explained. branch 8
In this case, since valid data with a different key address exists in the block in the data memory 20, the contents of the block (4 words) are first written back to the main memory. This process is the process in frame 101 in FIG. After securing the block to be written in this way, the data in the write data register 21 is written to the data cell at the specified address in the block in the data memory 20 in the process in box 102. In this case, the middle address section 32 is used to specify the block, and the lower address section 33 is used to specify the data cell within the block. Next, in the frame 103, the upper address part 3 is added to the key address part 13 of the directory memory 10.
Write the contents of 1 and select the directory in box 104.
Both the valid flag and the change flag in the memory 10 are rewritten to 1, the validation of the block is completed, and the process is terminated. In the process described here, the 4
Among the word data cells, for the three word data cells other than those written in the frame 102, the contents of the corresponding addresses are not read from the main memory as in the conventional example, so the contents of the corresponding addresses are not read from the main memory. The same block is enabled while the data from when the same block was used at the address remains. These three words of data are meaningless data for the user, but the write stack cache command is overwritten with the correct data when the subsequent write stack cache command is executed. is required to use. We will discuss in detail later how to use the cache command. FIG. 3 shows details of the processing contents of the frame 101. In order to write the contents of a block to the main memory, the four words in the block are read in sequence and sent to the main memory interface circuit 24 along with address information and a write control signal. In this case, counter 34 is used to generate the lower two bits of the address (equivalent to the data cell address within the block). Frame 1011 in Figure 3
First, the counter is cleared to zero, and the data selector 35, which normally selects the lower address section 33, is switched to the counter 34 side in the frame 1012. If the data memory 20 is read in the frame 1014 in this state,
The data cell specified by the output of the data selector 35 in the block specified by the middle address section 32 is read out. When this is sent to the main memory interface 24 via the cache data bus 23 and a main memory write control signal is sent to the main memory interface 24, the key of the directory memory 10 is used as the upper address for the main memory write. The values in the address field 13 are the same as those supplied to the data memory 20 as the middle and lower addresses, and are written into the main memory. After this, set the counter to 1 in frame 1015.
When the block 1014 is incremented by 1014 and the process in box 1014 is executed again, the contents of the next data cell in the block are written to the next address in the main memory. In this way, by repeating the processing in frames 1014 and 1015 four times, all the contents of the block will be written to the main memory, so
Finally, as post-processing, data selector 3 is selected in frame 1016.
5 is returned to select the lower address section 33, and the process is terminated. Although the processing of branches 5 and 7 in FIG. 2 is a cache miss, there is no need to write back the old data in the block to the main memory, so the processing of write back in frame 101 is removed from the processing of branch 8. are becoming equal. Each process in frames 81 to 83 is
The processing is the same as that of frames 102-104. The processing of branch 6 is the processing in the case of a cache human.
Since a data cell to be written already exists in the block, data is written in box 91 (same process as box 102), and the change flag is set to 1 in box 92, and the process ends. By introducing a control means that implements the write stack cache command described above, it is possible to use memory as a stack and write (push) data following the top of the stack.
When the CPU moves to the cache memory, the first
When writing the data of the second word, use the write shown in the conventional example as the cache command, and when writing the data after the second word, use the write stack cache command shown in this example. As a result, the number of unnecessary reads from the main memory can be reduced, and data writing can be performed faster. In this case, at first glance it appears that the write stack cache instruction can be applied to writing data in the first word, but it is only applicable when the address of the first word matches the beginning of the cache block. , otherwise the write
Application of the stack instruction may have the disadvantage that data previously stored on the stack and residing in main memory is not read into cache memory. Therefore, in this example, the write cache command is unconditionally used when writing the first word. Below, we will explain how to use the write stack command,
Using Table 2 and Figures 4 to 6, we will explain the state of data on the stack when data is written to the stack using this, and the number of data words transferred to and from main memory at that time. do.

〔Effect of the invention〕

According to the present invention, as described above, when a memory is used as a stack and data is continuously written to the leading end of the stack (especially when writing a memory larger than the block size of the cache memory), the main memory This has the effect of reducing unnecessary data reading from and shortening write time. For example, when interpreting and executing a LISP or PROLOG program using an interpreter written in firmware, a series of relatively large data is continuously written to the stack stored in main memory, such as when storing execution control information in the stack. In this case, the present invention is extremely useful because it can reduce the unnecessary reading of data from the main memory to the cache memory due to a cache miss, and shorten the time required to access the main memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cache memory device according to an embodiment of the present invention, FIG. 2 is a flowchart of a control procedure realized by the write stack control circuit of FIG. 1, and FIG. 4 to 6 are diagrams showing the state of data on the stack when data is written to the stack in the embodiment of the present invention, and FIG. FIG. 8 is a block diagram of an example of a cache memory device. FIG. 8 is a flowchart of a control procedure when write is specified as a cache command in a conventional cache memory device. FIG. FIG. 10 is a diagram showing details of the processing in box 75 in FIG. A diagram showing the state of data on the stack when writing out. Main code, 10...Directory memory, 11
...Valid flag section, 12... Change flag section, 13... Key address section, 14... Comparator, 20... Data memory, 21... Write data register, 22...
Read data register, 23... cache
Data bus, 24...Main memory interface, 30
...address register, 31...upper address section,
32... Middle address part, 33... Lower address part,
34...Counter, 35...Data selector, 41...Cache instruction register, 43...Control circuit, 44...
...control signal line, 46...cash command decoder,
47... Write stack cache instruction decoder, 50... Write stack control circuit, 51...
control signal line.

Claims (1)

[Claims] 1. When writing data, the data is written only in the cache memory, and when the written area is later used for cache access at another address, the data written in the area is written to the main memory. A write-swap type cache memory is provided with a first write control means and a second write control means, and when the memory is used as a stack and data is continuously written to the top of the stack, the first The first control means is used to start writing a word, and the second control means is used to start writing the second and subsequent words. If the block does not exist in the cache memory, after allocating the block in the cache memory, write data is written to the data cell at the address, and data for other data cells in the block is read from the main memory. The second control means executes a normal write swap control procedure for reading the data cell, and if the block containing the data cell at the write address does not exist in the cache memory, the block is cached. After allocating the data in memory, the write data is immediately written to the data cell at the corresponding address, and the block is enabled without reading data from the main memory for other data cells in the block. Characteristic memory control method.