JPH0115903B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk cache write control method in a disk subsystem within an information processing device.

Although the processing speed of intermediate processing units (hereinafter referred to as CPUs) has improved significantly in recent years, access times have not improved much since disk devices involve mechanical operations. As a result, disk input/output time has become one of the factors that restricts the performance of information processing systems. Therefore, a disk cache device has been proposed that is provided with a high-speed, small-capacity cache memory and stores some disk data in the cache memory to shorten the average disk access time.

In conventional disk cache devices, the following two methods are generally adopted for processing data written to the disk device.

The first method is to return a write operation end signal to the host device when the write data given from the host device such as the CPU is written into the cache memory, and then write the rewritten data to the disk. . This method has the advantage of shortening the write time when viewed from the outside, but it also handles problems when data cannot be written to the disk device due to a hardware failure etc. after returning the write operation completion signal. is extremely difficult. This is because the software of the central processing system that receives the write operation end signal determines whether the write operation has ended normally at that point, and if it is normal, it generally proceeds with the process. It is. In order to be able to handle write operation errors that are once determined to be normal, the operating system (OS) and fault handling software must be completely rewritten, which limits the application of disk cache. be done.

In the second method, the write data is written to the cache memory and also to the disk device.
This is a method in which a write operation completion signal is returned to the host device when the write operation to the disk device is completed.
According to this method, failure handling can be performed in the same way as without the disk cache memory, but the writing time remains the same as without the disk cache memory, and the effectiveness of the disk cache memory is halved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a disk cache write control method that eliminates the above-mentioned drawbacks and can shorten the apparent write time to a disk device without changing the fault handling software of the central processing system for the disk. There is a particular thing.

The device of the present invention includes a cache memory that stores part of the same data as the data recorded on the disk, and sends a write end signal when the write data for the disk given from the host device is written into the cache memory. This is configured by notifying the higher-level device of the data written in the cache memory so as not to write the data written in the cache memory to the disk.

Next, the present invention will be explained in detail with reference to the drawings. The information processing system shown in FIG. 1 to which the present invention is applied is comprised of a CPU 3000 including a channel, a disk device 2000, and a disk cache device 1000 including a disk control device. Note that the disk cache device 1000 does not necessarily have to be independent of the channel or disk control device, and can be incorporated into these devices. The disk cache device 1000 has a disk cache control device 400 and a cache memory 500, and the cache memory 500 stores part of the data from the disk device 2000. The disk cache control device 400 decodes commands for reading and writing data in the disk device 2000 given from the CPU 3000, and if the accessed data is in the cache memory 500, accesses the cache memory 500 and performs the access. If the stored data is not in the cache memory 500, the disk device 2000 is accessed and the cache memory 500 is updated as necessary.

FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 2, a disk cache device 1000
is a disk cache control device 400 that exchanges control information with the CPU 3000 via a signal line 410 and exchanges control information with a disk device via a signal line 420, and an address where the address of disk data accessed from the CPU 3000 is stored. a register 100, an upper limit address register 200 in which the upper limit address of a used file is stored;
The data section contains the data block of the disk, the address section contains the address of the data block on the disk, the V bit section becomes logic "1" when the data block contains valid data, and the data block is in temporary file mode. The cache memory 500 consists of a W bit section that becomes logic "1" when in use, the contents of registers 100 and 200, the address section of the cache memory block selected by the signal line 710, the V bit and the W bit. A comparison used by the disk cache controller 400 to determine whether the accessed disk block is in the cache memory, to select an empty block in the cache, to select a used block, etc. 700, and data buses 550, 560, and 570 connected to the CPU side, the disk side, and the data section of the cache memory.

Disk files can be broadly classified into permanent files and temporary files. Permanent files must have data recorded on a disk medium, but temporary files are files in which a data storage area is allocated on a disk medium for a short period of time, and when the file is finished being used, the allocated disk area is released. . Furthermore, due to the nature of temporary files, it is not essential that the data be written to the disk. In the present invention, for these two types of files,
One feature is that different control methods are adopted. That is, a mode register 401 is provided in the control device 400 in order to distinguish and control whether the data to be accessed is a temporary file or a permanent file. Information as to whether the file is a temporary file or a permanent file may be specified in an input/output command to a disk or a channel program, or may be specified by a separate control command.

Alternatively, an address range on the disk for files used in the temporary file mode may be registered in advance, and data included in this address range may be determined to be in the temporary file mode. The control device 400 sets the mode determined by these means in the mode register 401 each time a reading command is executed, and
Control is performed according to this mode. That is, first mode information is set in the register 401 in the permanent file mode, and second mode information is set in the register 401 in the temporary file mode.

Cache blocks used in temporary files are stored in cache memory until a release command is given from the CPU, as will be described later, so there is a possibility that the cache memory will be occupied by blocks in temporary file mode. In order to prevent this, the control device 400 includes a W block counter 402 that counts the number of cache blocks (blocks whose W bit is "1") that are used in the temporary file mode, and a A W block upper limit register 403 is provided for storing the W block, and temporary file blocks are allocated within the range of the upper limit value.

Next, the operation of the disk cache device of the present invention will be explained with reference to FIG.

To simplify the explanation below, it is assumed that data on the disk is recorded in fixed-length records called sectors, that the data address is represented by a volume number and a sector number within the volume, and that only one sector is recorded in one access. It shall be read and written.

It is assumed that one block of the cache memory 500 is 2 ⁿ times the size of a sector. First, the CPU
A case in which a permanent file mode read command is issued to the disk will now be described. The disk cache control device 400 stores the data address given from the CPU in the address register 100. The data address is device number 101, block number 102, and sector number 1 within the block.
04, the control device 400 has a comparator 700
Therefore, block address 10 of register 100
1 and 102 are compared block by block. Block selection line 710 starts with the first block in cache memory and advances one block at a time until the comparison results in a match. If the comparison matches (in this case,
(The V bit is always guaranteed to be logic "1") Indicates that the accessed block is stored in the data section of the cache memory block, and the accessed block is stored at sector address 104 from within the data section. The sector specified by the contents is transferred to bus 55.
0 and 560 to the CPU, and an input/output operation completion signal is transmitted to the CPU via the signal line 410.

If there is no match in the comparison, a command to read the block at block addresses 101 and 102 of the register 100 is sent to the disk device via the signal line 420, and the read block is transferred to the cache via the data bus 570. memory 5
Transfer to the preselected block of 00 and rewrite the address part to new addresses 101 and 102 V
Set the bit to 1. At the same time, the specified sector is sent from the data section to the CPU. Prior to this, it is necessary to select a replacement block in the cache memory.
0 is used to find a block in which both the V bit and the W bit are logic "0", and if found, that block is used as the replacement block. If such a block is not found, an appropriate block with low reference frequency is selected from among the blocks whose W bit is logic "0".
Typically, this selection involves selecting one of the candidate blocks that was least recently accessed (LRU) or most recently referenced (FIFO). What is important here is that blocks whose W bit is logic "1" are not eligible for replacement, and as explained later, this means that blocks using temporary file mode will remain in storage until the file is used. Saved in Tsushiyu memory.
Further, the V bit is referenced only when selecting this replacement block.

Next, in the case of a permanent file mode write command, the write sector data is transferred to buses 560 and 570.
is written to the disk device via. Similarly to the read command, the sector address of the write data is stored in the address register 100, and it is determined via the comparator 700 whether or not the block containing this sector is on the cache. (in which case the corresponding V bit of that block is guaranteed to be a logic “1”), sector data is also written to this cache memory block via buses 560 and 550. It will be done.

An input/output operation end signal to the CPU is transmitted via the signal line 410 when writing to both the cache memory and the disk device is completed.

Furthermore, when there is no write sector on the cache memory 500, the data is only written to the disk device, and the data is not written to the cache memory 500.
will not be updated.

In this way, in the case of permanent files, disk cache does not shorten the write time, but the data is always stored on the disk, and when a write failure occurs, the data is
The CPU is recognized, and therefore the necessary fault handling can be performed in the same way as if there were no disk cache.

Next, when a write command is output in temporary file mode, the sector address is stored in the address register 100 in the same way as described above, and it is determined whether or not there is an accessed block in the cache memory 500. If there is an accessed block on the cache memory 500 (in this case, the corresponding V bit of that block is guaranteed to be logic "1"), the sector is stored in the block of the cache memory 500. bus 56
Writes through 0 and 550. At this time, unlike permanent file mode, the cache memory is 500
At the end of writing to the CPU, the input/output operation end signal is sent to the CPU.
The write operation to the disk device is not performed.

If the addressed block does not exist on cache memory 500, controller 400
First, it is checked whether the W block counter 402 exceeds the upper limit value set in the W block register 403. If not, the comparator 700 is used to select an appropriate block from among the blocks whose W bit is logic "0". At the same time, the W bit of the selected block is set to logic "1", the value "1" is added to the W block counter 402, and the block addresses 101 and 102 of the register 100 are stored in the address field.
Data is written to the data section via buses 560 and 550 and its V bit is set to logic "1". At the end of this write, an input/output operation end signal is transmitted to the CPU, and no write operation is performed on the disk device.

If the value of the W block counter 402 exceeds the upper limit value 403, no cache block is allocated and the write data is transferred to the buses 560 and 5.
It is written only to the disk via the
be returned to.

Next, when a read command is output in temporary file mode, if the addressed sector is in the cache memory 500 (in this case, the corresponding V bit is guaranteed to be logic "1"). As in permanent file mode, the necessary sectors are read from the cache block and given to the CPU, completing the input/output operation.

If the addressed sector is not on cache memory, controller 400 reads the sector from the disk and sends it to the CPU via buses 570 and 560. At this time, unlike the permanent file mode, the cache memory is not updated.

Temporary files are first written to the disk, and then read from them. Therefore,
With the above control method, blocks are allocated to cache memory at the time of data writing, and
Only blocks that have not been allocated to cache memory are written to disk, and this allocation remains fixed for the duration of the file's use.

Next, a method for releasing blocks allocated to the cache memory at the end of file use will be explained.

When you finish using a temporary file, the CPU
specifies the disk address area used by the temporary file and outputs a cache memory release command to the control device 400. Upon receiving this command, the control device 400 sets the lower limit and upper limit of the specified block address in the address register 10, respectively.
0 and upper limit address register 200, and uses comparator 700 to determine which block in cache memory 500 has the address in register 10.
0 and 200 are found one by one, the V bit and W bit of the corresponding block are set to logic "0", and the value "1" is subtracted from the W block counter 402. If you repeat this operation for all cache blocks,
All cache blocks used by the specified temporary file are freed and become available for the next new allocation request.

The characteristics of the temporary file mode used in this invention are:
Blocks allocated to cache memory are written only to cache memory, which makes this invention more advantageous than a method in which data is also written to disk after the input/output operation end signal is returned to the CPU. The control becomes simpler and there is no problem of notifying the CPU of the error when a disk error occurs and it becomes impossible to write to the disk.

If it is not possible to write to the cache memory due to a failure of the cache memory, etc., the CPU will be notified as soon as the I/O operation end signal is received, so it will handle the error in the same way as when there is no disk cache. Just like in permanent file mode, there is no need to change the fault handling software.

In the above explanation, we assumed that the mapping between cache memory and disk data is fully associative (a method in which a disk data block can be assigned to any block in cache memory). It is also possible to group blocks into units called sets and perform mapping within the same set (set associative).

In addition, a program-controlled input/output processing device that can access the main memory of the CPU is installed separately from the CPU, and input/output processing such as preparing channel programs and executing input/output instructions is performed by this processing device instead of the conventional CPU. There are known functional sharing system configuration methods. In such a system, the various registers and control information of the above embodiments are stored in the local memory of the input/output processing device or the main memory of the CPU, and the various controls of the disk cache control device 400 are made to be performed by the input/output processing device. Can be done.

The present invention simplifies cache control by not recording the portion of temporary file data written to the cache memory on the disk, and eliminates the need to change failure handling software. This has the effect of shortening the writing time to the disk.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an information processing system to which the present invention is applied, and FIG. 2 is a diagram showing an embodiment of the present invention. 1 and 2, 400... disk cache control device, 500... cache memory, 100... address register, 200...
... Upper limit address register, 700 ... Comparator, 5
50,560,570...data bus, 300
0...Central processing unit, 2000...Disk device.

Claims (1)

[Scope of Claims] 1. A storage device comprising: a cache memory for storing a copy of a part of data recorded on a disk; and mode information storage means for storing first or second mode information given from the outside; If the first mode information is stored in the mode information storage means, at least after writing the write data from the host device to the disk, the host device is notified of a write end signal, and the mode information storage means is If the second mode information is stored, after writing the write data from the host device into the cache memory, the host device is notified of the write end signal and is instructed not to write to the disk. Features a disk cache write control method.