JPH03280084A - Control circuit for display device - Google Patents

Abstract

PURPOSE:To connect the liquid crystal display device by an interface similar to a multi-mode CRT monitor by incorporating an automatic detecting function for screen modes in a control circuit for liquid crystal display. CONSTITUTION:This control circuit is provided with a logic decision circuit 1 for a vertical synchronizing signal which consists of a 1st frequency dividing circuit 6 receiving a horizontal synchronizing signal HS as a count input and a vertical synchronizing signal VS as a start signal and a 1st latch circuit 7 receiving the vertical synchronizing signal VS as a data input and the output of the 1st frequency dividing circuit 6 as a latch input. Further, the screen mode decision circuit composed of a logic decision circuit 2 for the horizontal synchronizing signal which consists of a 2nd frequency dividing circuit 8 receiv ing a dot clock signal CK as a count input and the horizontal synchronizing signal HS as a start signal and a 2nd latch circuit 9 receiving the horizontal synchronizing signal HS as a data input and the output of the 2nd frequency dividing circuit 8 as a latch input is incorporated. Consequently, the liquid crystal matrix display device which provides the same feeling of use with the multi-mode CRT monitor can be constituted without placing any load on exter nal circuits nor the user.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to a device that is connected to a device having multiple screen modes such as a VGA mode, an EGA mode, and a CGA mode, such as an IBM personal computer, for example. The present invention relates to a display control circuit for a liquid crystal matrix display device that can be used as easily as a multi-mode CRT monitor.

[Summary of the invention]

The present invention provides a liquid crystal matrix display device with a large number of screen modes, for example, 6401480 dots, 640*3
The object of the present invention is to provide a control circuit for a display device that can automatically discriminate and display 50 dots, 1024*768 dots, etc.

[Conventional technology]

Conventionally, since the display device control circuit does not have a built-in function for automatically determining the screen mode, a command to switch the screen mode has been given to the display device control circuit or a mechanical switch has been used.

[Problems to be Solved by the Invention] However, in this method, in order to realize a multi-mode CRT monitor, it is necessary to control the control circuit for the liquid crystal display device in a personal computer etc. that supports the screen mode. It is necessary to add a function to
-Alternatively, a switch must be provided to manually select the screen mode at the expense of usage.
Furthermore, it is necessary to add a circuit for converting the logic of the horizontal synchronization signal and the vertical synchronization signal, resulting in a complicated system configuration.

[Step 1 to solve the problem! j] In order to solve the above problems, the present invention provides a display device control circuit with a circuit that automatically determines the screen mode from the signal logic state of the vertical synchronization signal and the signal logic state of the horizontal synchronization signal. It has become possible to configure a liquid crystal matrix display device that has the same usability as a multi-mode CRT monitor without putting a burden on the circuit or the user.

〔Example〕

The present invention will be explained below based on FIG. 1st
The figure is a circuit diagram of a control circuit for a display device according to the present invention. 1 The configuration of the control circuit for a display device is a vertical synchronization signal determination circuit 1, a horizontal synchronization signal determination circuit 2, a screen mode storage circuit 3, and a horizontal and vertical synchronization signal. It consists of a logic conversion circuit 4 and a liquid crystal control circuit 5 (not limited to liquid crystal use).

It should be noted that the vertical synchronizing signal discriminating circuit 1 consists of a frequency dividing circuit 6 and a latch circuit 7, and the horizontal synchronizing signal discriminating circuit 2 consists of a frequency dividing circuit 8 and a latch circuit 9.

The input signals connected to the display device control circuit are a vertical synchronizing signal (VS), a horizontal synchronizing signal (HS), a dot clock signal CK, and video signals R, G, and B (in the case of gradation display,
Each color consists of multiple dots).

The output signal from the liquid crystal control circuit 5 of the display device control circuit is the same as the signal of the simple matrix system, so it will be omitted.

Next, we will explain the circuit operation using Figures 1 and 2.1 For example, each screen mode of an IBM personal computer has a relationship as shown in Figure 2 between the logical states of the vertical synchronization signal and the horizontal synchronization signal. There is.

In summary, 640*350 dot screen mode: Vertical synchronization signal: negative logic, horizontal synchronization signal: positive logic 6401
480 dot screen mode: Vertical synchronization signal: negative logic, horizontal synchronization signal: negative logic 1024
*768 dot screen mode: Vertical synchronization signal: positive logic, horizontal synchronization signal: positive logic.

That is, the screen mode can be known simply by determining the signal logic of the horizontal synchronization signal and the vertical synchronization signal.

For example, the vertical synchronization signal determination circuit 1 detects a vertical synchronization signal (VS
) The frequency dividing circuit 6 starts counting the horizontal synchronizing signal (HS) from the rising edge TU. Then, for example, after 8 counts, the latch circuit 7 outputs the latch signal and the vertical synchronization signal (
VS) is stored in the latch circuit 7.

That is, if the signal level V is high level, the vertical synchronizing signal (VS) is determined to be negative logic, and if the signal level V is low level, the vertical synchronizing signal (VS) is determined to be positive logic.

Although not shown in the drawings, the horizontal synchronizing signal discriminating circuit 2 similarly starts counting the dot clock signal CK with the frequency dividing circuit 8 from the rising edge of the horizontal synchronizing signal (HS), for example. Then, for example, after 256 counts, a latch signal is output to the latch circuit 9, and the signal level of the vertical synchronization signal (HS) is stored in the latch circuit 9.

That is, if the signal level is high level, the horizontal synchronizing signal (HS) is determined to be negative logic, and if the signal level is low level, the horizontal synchronizing signal (HS) is determined to be positive logic.

The data in the latch circuit 7.9 is transferred to the screen mode storage circuit 3, and then output as a control signal to the horizontal/vertical synchronizing signal logic conversion circuit 4 and liquid crystal control circuit 5. The vertical synchronization signal VS and the vertical synchronization signal HS, which are output signals of the horizontal and vertical synchronization signal logic conversion circuit 4, are always converted to a constant logic state regardless of the screen mode. The liquid crystal control circuit 5 remembers one screen mode! 83, processing settings such as vertical screen position and horizontal screen position suitable for each screen mode are performed.

In the embodiments described above, the liquid crystal display control circuit is
The screen mode can be automatically detected from the horizontal synchronization signal, vertical synchronization signal, and dot clock signal, and the horizontal and vertical positions of the screen can be automatically set according to the detected screen mode.

〔Effect of the invention〕

As explained above, by incorporating an automatic screen mode detection function into a liquid crystal display control circuit, the present invention enables connection of a liquid crystal display device with an interface similar to a multi-mode CRT monitor, and facilitates connection. This has the effect of achieving an inexpensive system configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a display device control circuit according to the present invention, and FIG. 2 is a time chart of the display device control circuit according to the present invention. Vertical synchronization signal discrimination circuit Horizontal synchronization signal discrimination circuit Screen mode storage circuit Horizontal/vertical synchronization signal logic conversion circuit Liquid crystal control circuit

Claims (1)

[Scope of Claims] A liquid crystal matrix display device control circuit including a first frequency divider circuit that uses a horizontal synchronization signal as a count input and a vertical synchronization signal as a start signal, and a first frequency divider circuit that uses the vertical synchronization signal as a data input. The first circuit uses the output of the circuit as a latch input.
a logic discriminator circuit for a vertical synchronization signal consisting of a latch circuit; a second frequency divider circuit that also uses the dot clock signal as a count input and the horizontal synchronization signal as a start input; and a second frequency divider circuit that uses the horizontal synchronization signal as a data input; 1. A control circuit for a liquid crystal display device, comprising a built-in screen mode discriminating circuit comprising a logic discriminating circuit for a horizontal synchronizing signal comprising a second latch circuit whose latch input is the output of the frequency dividing circuit.