JP2654358B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly to a display control device for a liquid crystal display device which saves power consumption.

[0002]

2. Description of the Related Art An electronic apparatus having a display function for saving power of this type will be described with reference to the drawings.

FIG. 4 is a block diagram showing a conventional example.

In FIG. 4, this conventional example is disclosed in Japanese Patent Laid-Open No.
The contents disclosed in Japanese Patent No. 45295 are shown, and the user performs a key input using the keyboard 31. The entered key is
It is converted into key code data by the KBC 32 and temporarily stored therein, and notifies the interrupt controller 39 that a key input has been made. Upon receiving this notification, the interrupt controller 39 sends an interrupt command to the CPU 34. CP
When U34 receives the interrupt command, it reads the key code data from KBC32. Upon receiving the key code data, the CPU 34 converts the data into a character pattern and
Write 5 The display control circuit 36 performs the VRA operation at predetermined intervals.
The display data of M35 is read, and the data is sent to the display device 37. When receiving an interrupt command from the interrupt controller 39, the CPU 34 sends a reset signal to the timer 40. Upon receiving this reset signal, the timer 40 clears the counter and starts counting time again.

Here, the timer 40 sends a count completion signal to the CPU 34 after counting for a predetermined time. CP
U34 receives this signal and sends a VR to the display control circuit 36.
A control signal for suspending the reading of the display data of AM 35 is sent. The display control circuit 36 determines V based on the control signal.
Reading from the RAM 35 is stopped. As a result, the display data is sent to the display device 7 only when the display data is changed, so that the power consumption is reduced.

[0006]

In this conventional example, the CPU sends a control signal to the timer after receiving the interrupt command. When the timer counts a fixed period, the CPU sends a CPU count completion signal. Since the reading of display data is suspended, power consumption can be reduced.However, even if the display data does not change during the counting for a certain period of the timer, the power consumption cannot be reduced from the time when the display data changes. There is a problem.

[0007]

According to the present invention, there is provided a display control apparatus comprising: a VRAM for storing display data of a graph and a text from a host device; and a graph and a text based on the display data stored in the VRAM. In a display control device comprising a graph / text synthesizing circuit for synthesizing an image and an attribute synthesizing circuit for synthesizing an attribute signal including a black and white inversion of a display character and an underline with an output of the graph / text synthesizing circuit, the cursor does not change. And the display clock unit detects that no graph drawing signal has been generated from the host device and that there is no access to the VRAM for use other than the display data. If it is determined that there is no change in the data, the VRAM,
A display change presence / absence determining means for stopping transmission of a clock signal and a control signal to the graph / text combining circuit and the attribute combining circuit is provided.

A display control device according to the present invention is a VRAM for storing graph and text display data from a host device.
A graph / text synthesizing circuit for synthesizing the graph and the text based on the display data stored in the VRAM, and outputting an attribute signal including black and white inversion of display characters and an underline to the graph / text synthesizing circuit. An attribute synthesizing circuit, a cursor blinking detecting circuit for detecting that the cursor does not change during the period of disappearance of the cursor in units of display clocks, and a graph drawing signal from the host device not being generated. A VRAM access detection circuit that detects, in the display clock unit, that there is no access to the VRAM for use other than the display data from the higher-level device; A blinking detection circuit, the graph drawing detection circuit, and the RAM access is determined that there is no change in the display by receiving a detection signal from each detection circuit clock signal and the graphs to the VRAM
It has a text change circuit and a display change determination circuit that stops sending control signals to the attribute change circuit.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a display control device 1 according to the present embodiment is shown.
A VRAM 15 for storing graph and text display data from a host device; a graph / text synthesis circuit 16 for synthesizing graph and text based on the display data stored in the VRAM 15; An attribute synthesizing circuit 17 for synthesizing a tallibut signal including a line with an output of the graph / text synthesizing circuit 16, a cursor blinking detecting circuit 11 for detecting a period during which the cursor disappears and the cursor not changing,
A graph drawing detection circuit 12 for detecting that no graph drawing signal has been generated from a host device, a VRAM access detection circuit 13 for detecting that there is no access to the VRAM for use other than display data from the host device, and a cursor. Blinging detection circuit 11, graph drawing detection circuit 1
2 and the VRAM access detection circuit 13 to detect that there is no change in the display.
A display change determining circuit 14 for stopping transmission of a clock signal to the RAM 15 and control signals to the graph / text combining circuit 16 and the attribute combining circuit 17;
Display device 2 having CD buffer 21 and LCD 22
Connected to

In the cursor ringing detection circuit 11,
In order to determine the display parameter and blinking rate (blink cycle) on the text side, a command trace for the text side control and the blink cycle of the cursor are determined.
Thus, the display period, the disappearance period, and the blinking period of the cursor are determined, and it is detected that there is no change in the display of the text portion.

The transition of the circuit state is performed by the dot clock, but the state is unconditionally changed with respect to the reset.
The conditions for this state transition include (a) no change in GDC display & no access to text VRAM & cursor disappearance period (b) change in GDC display or access to text VRAM or cursor display period (c) reset There are three conditions. In addition, in the existing state, cursor blinking occurs immediately after the power-on reset, and thereafter, the state transits to the condition without car sublinking according to the condition (a). When one of the conditions (b) occurs, the state transits to a state with car sublinking.

FIG. 2 is a circuit diagram showing an example of the graph drawing detection circuit in this embodiment.

In FIG. 2, the graph drawing detection circuit 12 can monitor graph drawing by monitoring DBIN on the graph side. DBIN is VR from upper device
This signal is active when an access (read / write / modify) to the AM 15 occurs, whereby it becomes possible to detect when the contents of the VRAM 15 on the graph side change. Detection is performed by the dot clock,
The result is held for one image in the vertical direction at the screen display timing (vertical synchronization signal). The detected result is sent to the next stage in synchronization with the dot clock.

FIG. 3 is a circuit diagram showing an example of the VRAM access detection circuit in this embodiment.

In FIG. 3, the VRAM access detection circuit 13 can detect an access at the time of registering an external character in the VRAM 15 by monitoring an I / O write and a memory write from a host device. To synchronize the host device,
The detection and the result are performed in synchronization with the dot clock.

Next, the operation of state transition to the low power consumption mode of this embodiment will be described with reference to FIGS.

The condition for the state transition to the low power consumption mode in the present embodiment is that the cursor disappears from the output of the cursor blinking detection circuit 11 and the cursor does not change. When no drawing occurs, no access from the VRAM access detection circuit 13 to the VRAM 15 occurs, and when all the conditions are met, the display control device 1 transitions from the normal state to the low power consumption mode. In the low power consumption mode, the serial clock is stopped to stop the output of serial data from the display change determination circuit 14 to the VRAM 15. The operation of each of the text / graph synthesizing circuits 16 and the attribute data synthesizing circuit 17 is stopped by a control signal. In this case, since the display does not change, the power supply to the graph / text combining circuit 16 and the attribute combining circuit 17 can be completely stopped.

If any one of the above conditions is no longer satisfied, the display controller 1
Transitions from the low power consumption mode to the normal state. In this case, the display change determination circuit 14 sends the stopped serial clock again to the VRAM 15 to stop outputting the serial data. In addition, since the respective composition circuits have been stopped by the control signal for the text / graph composition circuit 16 and the attribute data composition circuit 17, the supply of power is restarted and each composition is resumed.

As described above, the low power consumption mode of the display control device 1 of the present embodiment can be executed in dot clock units.

[0022]

As described above, according to the present invention, the VRA for storing the display data of the graph and the test from the host device is provided.
M and a graph / text synthesizing circuit for synthesizing a graph and text based on the display data stored in the VRAM;
An attribute synthesizing circuit for synthesizing an attribute signal including a black-and-white inversion of a display character and an underline with an output of the graph / text synthesizing circuit; If no graph drawing signal is generated from the VRAM and there is no access to the VRAM for use other than display data, and it is detected in units of display clocks and it is determined that there is no change in the display data, the VRAM, graph
By providing a display change presence / absence determining means for stopping transmission of a clock signal and a control signal to the text synthesizing circuit and the attribute synthesizing circuit, power consumption is detected by detecting that the display does not change during counting for a certain period as in the related art. Since the state transition is made to the low power consumption mode in units of display clocks as compared with the case where the saving is performed, there is an effect that the power saving period can be executed earlier and longer than before.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a graph drawing detection circuit according to the embodiment.

FIG. 3 is a circuit diagram illustrating an example of a VRAM access detection circuit according to the present embodiment.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Display control apparatus 2 Display apparatus 11 Cursor blinking detection circuit 12 Graph drawing detection circuit 13 VRAM access detection circuit 14 Display change determination circuit 15 VRAM 16 Graph / text synthesis circuit 17 Attribute synthesis circuit 21 LCD buffer 22 LCD 121 AND circuit 122 OR circuit 123, 131 Flip-flop circuit (F / F)

Claims (2)

(57) [Claims] 1. A VRAM for storing display data of a graph and a text from a host device, a graph / text combining circuit for combining the graph and the text based on the display data stored in the VRAM, and a display. A display synthesizing circuit for synthesizing an attribute signal including a black-and-white inversion of a character and an underline with an output of the graph / text synthesizing circuit; The VRAM for use other than the display data when no graph drawing signal is generated from the device
When it is detected that there is no access to the display clock unit, and it is determined that there is no change in the display data, the transmission of the clock signal and the control signal to the VRAM, the graph / text synthesizing circuit and the attribute synthesizing circuit is performed. A display control device comprising a display change presence / absence determining means for stopping. 2. A VRAM for storing graph and text display data from a host device, a graph / text synthesis circuit for synthesizing the graph and text based on the display data stored in the VRAM, and a display character. An attribute synthesizing circuit for synthesizing an attribute signal including a black-and-white inversion and an underline with the output of the graph / text synthesizing circuit; A detection circuit for detecting the absence of a graph drawing signal from the host device in clock units of the display, and an access to the VRAM for use other than the display data from the host device. VRAM access detection to detect that there is no Output circuit, the cursor blinking detection circuit, the graph drawing detection circuit, and the VRAM
A display for receiving a detection signal from each of the access detection circuits, determining that there is no change in display, and stopping transmission of a clock signal to the VRAM and a control signal to the graph / text synthesis circuit and the attribute synthesis circuit. A display control device comprising: a change determination circuit.