KR920008958B1 - Display control apparatus - Google Patents

Abstract

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Description

Display control device

1 is a block diagram showing the overall configuration of one embodiment of the present invention.

2 is a block diagram showing the configuration of main parts of the embodiment;

3 is a timing diagram showing the operation of the embodiment;

4 is a block diagram showing the overall configuration of a conventional example.

5 and 6 are block diagrams showing the main parts thereof.

7 is a diagram showing a screen configuration of a display device.

8 and 9 are timing diagrams showing the operation of the conventional example.

* Explanation of symbols for the main parts of the drawings

1: display controller (CRTC)

2: display data storage (VTAM; first storage means)

3, 4: display data holding circuit (F / F)

5: memory for generating display data (CG; second storage means),

6: image data generating circuit (DGL; image data generating means)

7: Display device (CRT) 8: Main device side character code holding circuit (F / F)

9: selector

10: Memory access circuit (DCNT; access means) for generating display data

10b: display timing detection circuit 10d: through latch (character pattern data holding means)

11: Display data storage access circuit (VRIF)

12: access mode detection circuit 13: display mode detection circuit

The present invention relates to a display control device which makes it possible to control the access of the display data generation storage device by the main device (for example, the system side CPU in a personal computer system) by the display mode.

4 is a block diagram showing the overall configuration of a conventional display control apparatus, (1) a display controller (CRTC), (2) a display data storage device as first storage means for storing display data ( VRAM), (3) and (4) are display data holding circuits (F / F) for temporarily holding display data read from the VRAM (2), and (5) second storage means for storing character pattern data. Display data generation memory CG, 6 denote image data generation circuit DGL, 7 denote display CRT, and 8 denote character main data held by the main character. The character code holding circuit F / F has a counter for counting the number of bytes of character pattern data corresponding to one character code. (9) is a selector which selects one output of F / F (3) and F / F (8) and inputs it to CG (5), and (10) is display data for accessing CG (5) from the main apparatus side. A generation memory access circuit (DCNT), which has a flip-flop (F / F) 10a of an edge trigger as means for holding character pattern data. Numeral 11 denotes display data storage device access circuit VRIF, symbol 12 denotes access mode detection circuit, symbol 13 denotes display mode detection circuit.

5 shows the configuration of the image data generation circuit (DGL) 6 in detail. In the figure, 6a is a graphic / image converter, 6b is a character attribute data holding circuit, 6c is a character pattern bottle / serial converter, 6d is a text image selector, and 6e is a border. The color registers 6f are image data selectors.

6 shows the configuration of the display data generation memory access circuit (DCNT) 10 in detail. In the figure, reference numeral 10a denotes flip-flops F / F and 10b for holding character pattern data described above, and a display timing detection circuit, and 10c, a data fetch timing generation circuit.

Next, the operation of FIG. 4 will be described. The CRTC 1 outputs a signal for controlling the display device, a control signal for reading the display data of the VRAM 2 or timing signals to the DGL 6 and the DCNT 10. In the main apparatus, the display data is sent to the VRAM 2 and written via the VRIF 11. The CRTC 1 accesses the VRAM 2 and reads its data, and the read data is temporarily held in the F / F 3 and F / F 4. Subsequent operations vary depending on the display mode. In the display mode, there are other graphics display modes other than the character display mode and the character display mode. In the character display mode, the character code data (character code data) is displayed in the F / F (3), and the F / F (4) is displayed. Character attribute data (attribute data) is maintained. The selector 9 normally selects the output of the F / F (3). The selector 9 inputs the character code data from the F / F (3) to the CG (5) via the selector (9), and the corresponding character pattern. Data is output from the CG 5. The character pattern data and the character attribute data from the F / F 4 are input to the DGL 6, and the DGL 6 generates image data from those data and outputs it to the CRT 7. In the graphics display mode, the outputs of the F / F (3) and F / F (4) are directly input to the DGL (6), and image data is generated and output to the CRT (7). A signal is sent from the display mode detection circuit 13 to the DGL 6 to switch between text image data and graphics image data.

Specifically, using Fig. 5, in the graphics display mode, the graphics data is contained in the VRAM 2, and the data is temporarily held in the F / Fs 3 and 4 so that the graphics image bottle can be used. To the serial converter 6a, graphics image data is generated and input to the image data selector 6f. In the character display mode, the character data is contained in the VRAM 2, the character code data is held in the F / F 3, and the character attribute data is held in the F / F 4 as described above. The CG 5 is accessed via the selector 9 by the output of the F / F 3, and the read character pattern data is held in the character pattern bottle / serial converter 6c. On the other hand, the character attribute data from the F / F 4 is held in the character attribute data holding circuit 6b and input to the character image selector 6d. In the character image selector 6d, the character color data and the background color data in the character attribute data are selected by the output of the character pattern bottle / serial converter 6c and input to the image data selector 6f. The border color register 6e contains data for determining the display color of the border area. As shown in FIG. 7, the image area 7a on the screen of the CRT 7 is composed of the display area 7b and the border area 7c which is the border of the display area 7b, and is displayed by the CRTC 1. A signal for selecting whether the area 7b or the border area 7c is input is switched to the image data selector 6f. In addition, a signal indicating the display mode is input from the display mode detection circuit 13, and the image data selector 6f selects whether to output graphics image data or character image data to the display area 7b.

Next, the operation when the main apparatus accesses the CG 5 will be described.

8 shows the timing signal DE input from the CRTC 1 to the display timing detection circuit 10b in the DCNT 10. As shown in FIG. In the access mode, the access mode I for allowing access to the CG (5) of the main apparatus only in the non-display period t2 and the two periods of the display period t1 and the non-display period t2, that is, the access mode II for always allowing access to the CG (5) of the main apparatus There are two types, which are set in the access mode detection circuit 12. In both modes, data is input to the CG 5 from the F / F 8 by writing the character code data from the main device to the F / F 8, and the corresponding character pattern data is output. The data is transmitted to the main device fetched by the DCNT 10 by the timing signal of the CRTC 1. On the contrary, it is also possible to send the character pattern data to the CG (5) from the main device, and to write the character code data to the F / F (8) and the character pattern data to the DCNT (10), the CRTC (1). The character pattern data is sent to the CG 5 by the timing signal of. However, in the character display mode, the CG 5 inputs the character code data, which is the output of the F / F 3, via the selector 9 to generate the display data during the display period. Must be sent to DGL (6). Therefore, of the two access modes, the access mode I permits access to the main apparatus only in the non-display period t2. However, the non-display period t2 is short as one-minute of the display period t1, so that the access performance is poor. In the other access mode II, if there is access from the main apparatus even during the display period, the access performance is improved by bringing the selector 9 to the F / F 8 side, but the data of the main apparatus is transferred to the DGL 6 during the display period. Also, the image is disturbed because it is transmitted.

It demonstrates concretely using FIG. Since the access mode I only prohibits the access during the display period in the access mode II, the access mode II will be described. 9 is a timing signal α obtained by dividing the character clock input from the CRTC 1 into two, and is generated by the data fetch timing generation circuit 10c. First, the display mode detection circuit 13 sets the character display mode and sets the access mode II to the access mode detection circuit 12. Next, the character device writes the character code data to the F / F (8). The character code data is written to the F / F 8 at the rise of the timing signal α, and the selector 9 outputs the data of the F / F 8 to the CG 5. The CG 5 outputs corresponding character pattern data accordingly, and is input to the flip-flop 10a. This character pattern data is held in the flip-flop 10a when the timing signal alpha falls, and the main device reads this holding data. On the other hand, the counter in the F / F 8 counts up as the timing signal α falls. Since the character pattern data is composed of several bytes per character, after setting one character code, it is necessary for the main apparatus to read those bytes, and setting the number of bytes is a counter in the F / F (8). . If the main device does not read data entered in the flip-flop 10a, the data holding clock of the new CG 5 is not outputted from the data fetch timing generation circuit 10a by the flip-flop 10a, so that the flip-flop 10a Data is retained, and data transfer is normally performed to the main device. In order to read the data of the flip-flop 10a, a command (I / 0 read signal, etc.) is output from the host device and executed.

When the display mode is the graphics display mode, the CG 5 is accessed in the same manner as described above. However, in the graphics display mode, the CG 5 is not required directly from the graphics image data. Accessibility is also improved because it is not disturbed. However, also in this case, when the data is written to the F / F 8 and then the character pattern data is read, the timing at which the data enters the DCNT 10, and when the data is written to the CG 5, the CRTC ( It is executed by the timing signal of 1).

Since the conventional display control device is configured as described above, even when the character display mode does not require the CG 5, the read / write access to the CG 5 of the main device is performed by the timing signal of the CRTC 1. There is a problem in that the timing is restricted and the access performance is reduced by that.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and in modes other than the character display mode, access from the main device to the second storage means for storing character pattern data can be executed without any timing limitation. To obtain a display control device. The display control device according to the present invention comprises the character pattern data holding means as a through latch, and when the character is out of the character display mode, the timing is generated by generating the timing according to the access command in the main apparatus regardless of the timing in the display controller. It is provided with the timing generation means to control.

The display control apparatus according to the present invention uses the character pattern data holding means as the through latch, and at the same time, in the display mode in the character display mode, at the timing of the display controller in the character display mode, and in the main apparatus when the character is out of the character display mode. By controlling at the independent timing in the timing generating means according to the access command, in modes other than the character display mode, the access means for accessing the second storage means from the main apparatus is completely separated from the display timing, and the access from the main apparatus is disconnected. Run at high speed.

EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of this invention is described according to drawing. In addition, the same code | symbol is attached | subjected to the same or corresponding part as the said prior art example, and the description is abbreviate | omitted.

1 is a block diagram showing the overall configuration of an embodiment. As shown in FIG. 1, a through latch 10d is provided as a character pattern data holding means in the storage device access circuit (DCNT) 10 for generating display data, and the output of the display mode detecting circuit 13 is a selector. Also inputted to (9), the selector 9 selects the output of the F / F 8 in modes other than the character display mode.

2 shows the configuration of the DCNT 10 in detail. As described above, the DCNT 10 has a character pattern data holding means composed of a through latch 10d, and the data fetch timing generating circuit 10e is different from the conventional one. Irrespective of the timing signal of FIG. 3, the data fetch signal corresponding to the command signal (for example, I / 0 read signal) in the main apparatus is generated and output as shown in FIG.

Next, the operation will be described.

In the conventional apparatus, when the main apparatus executes access to the CG 5, the DCNT 10

Character pattern data holding means is composed of a flip-flop (F / F) 10a of an edge trigger. Therefore, a data fetch timing signal is always required to send and receive data, and the CRTC (1) generates the timing signal. It is running under the control of). On the other hand, in the present application, instead of the flip-flop 10a of the edge trigger, the through latch 10d is used. Flip-flop of edge trigger (1

In the case of 0a), the output signal changes due to the rise of the timing signal, but in the case of the through latch 10d, the input appears as an output as it is when the timing signal is ＂H＂, and data is retained at the fall. Use this function.

In the character display mode, as in the conventional example, both the access modes I and II are subject to the timing constraints of the CRTC 1, and in the access mode II, the images are scattered. However, in modes other than the character display mode, that is, a mode in which the CG 5 is not directly required for generating image data such as a graphics display mode, the asserted value is not accessible to the CG 5 without being subject to timing control of the CRTC 1. Can be. That is, when the display mode detecting circuit 13 recognizes that the display mode is other than the character display mode, the selector 9 selects the F / F 8 side and outputs it to the CG 5. In addition, DCNT (10

), The timing signal of the through latch 10d is fixed to ＂H＂. In other words, the through latch 10d becomes a simple gate, and the input is outputted as it is. Therefore, the main device and the CG 5 become the same as those directly connected, and are not subject to any timing constraints. That is, the CG 5 is completely separated from other circuits for image generation, and can be freely accessed by the main device as a simple storage device.

The above is explained concretely using FIG. Since the character display mode is the same as that of the conventional example as described above, other than that, the graphic display mode is explained.

The graphics display mode is set in the display mode detection circuit 13, and the data fetch timing generation circuit 10e is completely separated from the display timing detection circuit 10b and the CRTC 1. The access mode detection circuit 12 is ignored even if either of the access mode I and the access mode II is set. The assertion value first sets the character code data in the F / F (8). Next, a command (a command for fetching data of the CG 5) is output to the data fetch timing generation circuit 10e. Since the command width T (see FIG. 3) is greater than the access time of the CG 5, the character pattern data of the CG 5 is input to the through latch 10d. In this mode, the CG (5) data fetch signal from the data fetch timing generation circuit 10e to the through latch 10d is " H ", so the latch latch 10d function does not operate and only the gate function operates. do. In other words, when the command signal is output from the main device, the CG (5) data fetch signal from the data fetch timing generation circuit 10e becomes HH, and the gate of the through latch 10d is opened to transmit data to the main device. On the other hand, the counter in the F / F (8) counts up when the command signal rises, that is, when the CG (5) data fetch signal falls.

As described above, in the conventional example, access to the CG 5 from the main device controlled at the timing of the display control device is not stored at all in the above timing constraints in the present application, and can be accessed as a general storage device. Further, in the above embodiment, the CG 5, i.e., the storage device for generating display data, is shown as the second storage means, but the present application is also applicable to the display data storage device distinguished for each display mode.

According to the present invention as described above, the character pattern data holding means is constituted by a through latch, and when the character pattern data is out of the character display mode, the timing is generated by generating the timing according to the access command of the main apparatus regardless of the timing of the display controller. A timing generating means for controlling is provided, and when the claim value is other than the character display mode, the claim value is configured so that the second storage means can be accessed as a simple storage device without any other restriction, thereby increasing the access performance of the second storage means. At the same time, the performance improvement including claims can be achieved.

Claims (1)

A display controller (1) coupled to a main device for generating a display timing signal, first storage means (2) coupled to the display controller for storing display data, and coupled to the display controller and the first storage means It is coupled to the second storage means 5 for storing data, the display controller and the first storage means, the second storage means and the display device 7, and in the character display mode, the first and second storage means. Image data generating means 6 for outputting image data according to the data of the storage means to the display device and outputting image data according to the data of the first storage means to the display device when the display device is out of the character display mode. A controller has character pattern data holding means coupled to the second storage means, and access from the main device to the second storage means is dependent on the display mode and the timing from the display controller. In the display control apparatus provided with the access means 10 which performs through the said character pattern data holding means, WHEREIN: The character pattern data holding means 10d of the said access means comprises a through latch, and the said main apparatus and display control And timing generation means (10e) coupled to the through latch and generating timing according to an access command from a main apparatus when the display controller is out of the character display mode, regardless of the timing from the display controller. Display control device characterized in that.

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