KR0148894B1 - Graphic accelerator - Google Patents

Abstract

According to the present invention, when a large amount of data is input to video memory for a high resolution graphic application or moving picture in a personal computer, a graphics for preventing performance degradation due to a bottleneck of video memory. It is related to an acceleration system. In a general graphics system, an operation in which a CPU writes information to a video memory and a VGA graphics control for displaying data stored in a video memory are linked to each other. The problem of degrading graphics display performance due to insufficient allocation of time for writing data. In the present invention, when the data is accessed to display data in the video memory, the data that the CPU intends to write to the video memory is displayed. If it matches with the address of the data to be checked, if it is matched, the data is written to the video memory and the data is displayed immediately, so that the display access to the video memory and the data recording by the CPU are simultaneously performed. The recording time is not required separately, and the data recording by the CPU is recorded in the internal PIPO, which reduces the load on the CPU during data recording, thereby improving the performance of the display and data recording operations of the graphic system. Becomes

Description

Graphics acceleration system

1 is a block diagram of a general graphics acceleration system.

2 is a block diagram of a graphics acceleration system of the present invention.

FIG. 3 is a connection diagram illustrating an address comparison and control signal generator and peripheral circuits in FIG. 2.

4 (a) is a detailed circuit diagram of the register and the comparison unit in FIG.

4B is a detailed circuit diagram of the control signal generator in FIG. 3.

* Explanation of symbols for main parts of the drawings

1: Video memory 10: Bus interface unit

20: drawing coprocessor 21: data pipo

22: address pipo 30: memory control and interface unit

40: VGA graphics control unit 50: CRTC

60: display control unit 61: display pipo

62: VGA property control 70: Hardware cursor

80: digital analog converter 90: clock generator

100: address comparison and control signal generation unit 110: data register

120: register 120A: first register

120B: second register 130: comparison unit

131: first flip flop 132: second flip flop

EX1: First Exclusive Oagate EX2: Second Exclusive Oagate

OR1: first OA gate 140: control signal generation unit

141: mux 142: third flip-flop

143: fourth flip-flop 144: fifth flip-flop

145: 6th flip-flop OR2: second oragate

OR3: third OA gate OR4: fourth OA gate

AND1: ANDGATE

According to the present invention, when a large amount of data is input to video memory for a high resolution graphic application or moving picture in a personal computer, a graphics for preventing performance degradation due to a bottleneck of video memory. Relates to an acceleration system.

In general, the configuration of a graphics system that reads data input to the video memory and displays it on a monitor screen while inputting video data into the video memory is configured as shown in FIG. 1.

That is, a bus interface unit 10 for interfacing data and control signals from a central processing unit (hereinafter referred to as a CPU) via an ISA (Instrument Society of America), an EIAS (Electronic Industries Association Standard), and a local bus. )Wow; A clock generator 90 generating a reference clip of the system; Drawing coprocessor for temporarily storing the data SD input from the bus interface unit 10 or processing the data of the video memory 1 (Color Extention, Block Transfer, Polygon fill, Line Draw, etc.) 20); A memory control and interface unit 30 for accessing (reading / writing) data stored in the video memory 1; It consists of General Register, Sequence Register, and Graphic Control Register, and stores data SD in various registers through the various interface units 10 to control modes, control characteristics, A VGA (Variable Gain Amplifier) graphics control unit 40 which controls a memory mode, a graphics map clock mode, and the like; The VGA graphics controller 40 stores information about a resolution corresponding to a mode selected by counting the video clock output from the clock generator 90 to generate a reference typing of the displayed data, thereby generating a cathode ray tube. Cathode ray tube control unit (hereinafter referred to as CRTC) 50 for controlling the; Inputting the display data MD of the video memory 1 input through the memory control and interface unit 30 and combining the VGA attributes thereof to convert the pixel data PD to the CRTC 50. A display controller 60 for outputting according to the timing of the display; A hardware cursor (70) for indicating, as a cursor, a position at which display data (MD) is to be displayed from the memory control and interface section (30); A digital analog converter (hereinafter referred to as a DAC) that inputs digital pixel data PD from the display controller 60 to convert an analog signal and outputs various color signals R, G, and B (80). It is configured to include).

A brief description of the operation of a general graphics system configured as described above is as follows.

When the CPU writes data to the video memory 1 via the bus interface unit 10 to display any information, the recorded information is accessed by the VGA graphics control unit 40 at the timing generated by the CRTC 50. The DAC 80 is then displayed on the monitor screen.

However, since the data access priority in the video memory 1 is on the display, the graphics system reads the data to be displayed in the page mode from the video memory 1 in the page mode and displays the data that the CPU wants to input from the CPU during the display time. It is recorded in the memory 1. At this time, when the display of the data read out from the video memory 1 is completed, the data input operation to the video memory 1 by the CPU makes a rest until the reading operation of the data performed from the next address of the displayed data is completed. . While doing so, the CPU enters data into the bit memory 1 only.

For example, the data displayed at a certain resolution is data stored at address 0 to 500 of the data stored in the video memory 1, and the CPU stores new data from address 50 to 130. In order to display by inputting, the display operation in priority is first read the data stored in the video memory (1) in the page mode, and stored in the display pieo 61 included in the display control unit 60 to display During the display operation, the CPU sequentially writes data corresponding to address 130 from address 50 to be input. At this time, when the display of the data read in the display piepo 61 is completed, the input operation is stopped in the middle, and the data to be displayed is read in the page mode in order. As described above, when the above operation is continuously performed, the CPU writes the data of the video memory 1 to input data into the video memory 1 and the data of the video memory 1 to display the data. The read operation is not done at the same time.

In order to describe the operation in more detail, the configuration of FIG. 1 will be described.

When the data stored in the video memory 1 is to be displayed from the CPU, in order to be displayed by inputting new data to a range of addresses, the data SD to be stored in the video memory 1 from the CPU and the corresponding address (SA) are displayed. Decode the address SA entered via ISA, EIAS, local bus to see if it is a given area in video memory 1. If the address SA is a region corresponding to the video memory 1, the input data SD and the address SA are inputted from the bus interface unit 10, and the data SD to be stored is the drawing coprocessor 20. The address SA is output to the drawing coprocessor 20 and the memory control and interface unit 30.

The drawing coprocessor 20 having inputted the address SA of the data SD to be stored above is stored in a buffer configured therein until recorded in the video memory 1. Then it sends an acknowledgment signal to the CPU. In addition, the address SA stored in the buffer is converted into an address of the video memory 1, and the first input address is input to the memory control and interface unit 30.

Meanwhile, the VGA graphics controller 40 stores information in various VGA registers, and the CRTC 50 stores information about the resolution of the mode selected by the VGA graphics controller 40 to generate display reference timing. In this way, the VGA graphics controller 40 outputs the address MA of the display data MD to be displayed on the computer to the video memory 1 through the memory control and interface unit 30 according to all the stored data information. To access the video memory 1 continuously. Then, the data of the video memory 1 accessed by the VGA graphics controller 40 is input to the display pieo 61 of the display controller 60, and the display pieo 61 performs a buffer buffer function and the CRTC. In synchronization with the display reference timing generated in accordance with the respective resolutions at 50, the data in the display piepo 61 is output to the DAC 80 as pixel data PD. The DAC 80 converts the signals into analog signals and displays them on the monitor screen as various color signals (R.G.B).

In the video memory 1 of the graphics system configured as described above and operating in graphics, the priority of the access to the recorded information is on the display side, so that the VGA graphics control unit 40 may display the video in order for the CPU to update the information. In order to process a large amount of data at a high resolution, even if the CPU is supplied quickly, the video memory (1) does not update properly at that speed, and graphics performance is degraded. do.

In other words, the CPU writes some information into the video memory and the VGA graphics control unit displays the data stored in the video memory, which is sufficient to record the data from the CPU to the video memory. Not allocating time reduces graphics display performance. This phenomenon is called a bottleneck of video memory.

In view of this, the present invention, when accessing to display the data in the video memory, the CPU checks whether the data to be recorded in the video memory matches the address of the data to be displayed, if it matches, writes to the video memory and at the same time the data By directly displaying, the display access to the video memory and the data recording by the CPU are simultaneously performed.

In order to satisfy the above features, the configuration of the present invention allows the data to be recorded in the video memory to be displayed simultaneously with the recording in the video memory without regard to the display operation.

In the configuration of a general graphics system, a PIPO which stores data and an address to be recorded in the video memory by connecting to a drawing coprocessor which inputs data by the CPU through the bus interface unit and temporarily stores the data to be input into the video memory. And compare the address stored in the PIPO with the address of the data in the video memory to be accessed and displayed by the VGA graphics control unit and, if there is a match, the address comparison for displaying the data stored in the PIPO and writing to the video memory at the same time. By configuring the control signal generation unit in conjunction with the memory control and interface unit, data recording by the CPU and display access to the video memory are simultaneously performed.

The address comparison and control signal generation unit registers and sequentially stores one address stored in the address pipo; A comparison unit which compares an address of data to be accessed and displayed by the VGA graphics control unit with an address input from the register and compares the address; A data register that is enabled according to the output state of the comparator and inputs data from the data pipeo to be simultaneously displayed in a video memory through a memory control and interface unit; The video memory read signal is converted into a video memory write signal so that the data of the data register is written to the video memory according to the output signal of the comparator, and outputs to the memory control and interface unit while there is no input of data into the register and the data register. And a control signal generator for inputting the data and address of the data and address PIPO to the register and the data register when the PIPO write signal is input by the CPU in the initial state.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a configuration of the present invention graphics acceleration system.

A bus interface unit 10 for interfacing data and control signals from the CPU via ISA, EIAS and local buses; A clock generator 90 generating a reference clock of the system; A drawing coprocessor (20) for temporarily storing data (SD) input from the bus interface unit (10) or processing data of the video memory (1) (Color Extention, Block Transfer, Polygon fill, Line Draw, etc.); A data piepo 21 and an address piepo 22 for storing data and an address by the CPU input from the drawing coprocessor 20, respectively; A memory control and interface unit 30 for accessing (reading / writing) data stored in the video memory 1; It is composed of general register, sequence register, and graphics control register, and stores data SD in various registers through the various interface units 10 to control modes, control characteristics, and A VGA graphics control unit 40 for managing a memory mode, a graphics map clock mode, and the like; The VGA graphics controller 40 stores information about a resolution corresponding to a mode selected by counting the video clock output from the clock generator 90 to generate a reference timing of the displayed data, thereby generating a cathode ray tube. CRTC 50 for controlling the; The display data MD of the video memory 1 input through the memory control and interface unit 30 is input, and its VGA attributes are combined to output the pixel data PD according to the timing of the CRTC 50. A display control unit 60; A hardware cursor (70) for indicating, as a cursor, a position at which display data (MD) is to be displayed from the memory control and interface section (30); A DAC (80) for inputting digital pixel data (PD) from the display control unit (60), converting it into an analog signal, and outputting various color signals (R, D, B); A clock generator (90) for generating a reference clock for memory access and display timing by the circuits; The address FA stored in the data pipeo 21 and the address pipeo 22, respectively, and the address of the data to be accessed and displayed by the VGA graphics control unit 40 are compared and the data pipeo according to the match. And an address comparison and control signal generator 100 for displaying the data FD stored in the 21 in the video memory 1 while displaying the data FD through the memory control and interface unit 30 at the same time.

In the above configuration, the configuration of connection between the address comparison and control signal generator 100 and the peripheral circuits is the same as that of FIG.

First, the configuration of the address comparison and control signal generator 100 will be described.

A register 120 for inputting an address FA from an address pipeo 22 that stores the corresponding address SA of the data SD by the CPU; The display address MA and its row address strobe signal RAS of the next data to be displayed from the VGA graphics control unit 40 are inputted to display the address MA and the address by the register 120. A comparator 130 for comparing FA) and outputting a signal according to whether there is a match; The video memory is enabled according to the output signal COM1 of the comparator 130 to display the data FD input from the data pipeo 21 on the monitor screen through the memory control and interface unit 30. A data register 110 for writing to (1); Read output from the memory control and interface unit 30 so that the data MD output from the data register 110 can be recorded in the video memory 1 according to the output signal COM1 of the comparator 130. The output signal COM1 of the comparator 130 and the column address strobe signal CAS of the display address MA output from the VGA graphics controller 40 are converted while converting the signal RS into the recording signal WS. When a PIPO write signal is input by the CPU in an initial state in which no data is input to the register 120 and the data register 110, the data and address pi is input to the register 120 and the data register 110. And a control signal generation unit 140 for outputting a PIPO read signal FR so that the data FD and the address FA of the fabrics 21 and 22 are input.

The present invention configured as described above operates as follows.

That is, when the CPU wants to write data to the video memory 1 via the bus interface unit 10 in order to display some information, the drawing coprocessor inputting the system address SA and data SD from the CPU ( 20 converts the system address SA into an address FA that is the same as the address format of the video memory 1, and converts the address FA and the corresponding data FD into the respective data and address pipeo 21. Store in (22). Then, the operation termination signal is sent to the CPU to reduce the load on the CPU. At this time, the data to be written by the CPU is in the standby state in the data pipeo 21. The larger the size of the data pipeo 21 storing the data FD is, the more data can be stored. Performance is improved.

Meanwhile, in order to display the information recorded in the video memory 1, the VGA graphics controller 40 accesses the video memory 1 and outputs display data MD. In this case, the address comparison and control signal generator In operation 100, the address FA stored in the address pipeo 22 is the value stored in the register 120 and the display address MA output by the VGA graphics controller 40 to access the video memory 1. If the values are the same, the data register 110 is enabled to output the data FD input from the data pipo 21 to the memory control and interface unit 30, and the video memory read signal RS is output. The data MD output to the memory control and interface unit 30 is converted into the video memory recording signal WS so as to be recorded in the video memory 1. In addition, since the data MD of the memory control and interface unit 30 output from the data register 110 corresponds to the display address MA output from the VGA graphics control unit 40, the data MD of the memory control and interface unit 30 is stored in the video memory 1. It is recorded and displayed on the monitor screen. This enables the CPU to record data in the video memory 1 without allocating time for separately recording the data in the video memory 1.

If the comparison value does not match, the display memory (MD) corresponding to the display address (MA) is read by accessing the video memory (1) in the same manner as the general display operation, and then combined with the VGA attribute in the display controller (60). Be sure to Then, the generated pixel data PD is output to the DAC 80 according to the timing generated by the CRTC 50 to be output to the monitor screen as an analog signal.

4 (a) and (b) show the detailed circuit configuration of the address comparison and control signal generator 100 of FIG. 3, and (a) shows the circuit diagram of the register and the comparator 120 and 130. And (b) is a circuit diagram of the control signal generator 140.

The operation of the address comparison and control signal generator 100 will be described in more detail with reference to the following.

First, when the VGA graphics controller 40 outputs the display address MA to the comparator 130 to display data stored in the video memory 1, the row address RA is a row address strobe signal. (RAS) is latched on the first flip-flop 131, while eight bits of the address FA stored in the address pipeo 22 are inputted to the first register 120A and the first flip-flop 131 is closed. It is input to the first exclusive oracle EX1 together with the address latched at. At this time, when the two addresses match, the output value P1 of the first exclusive oragate EX1 becomes '0'.

The column address CA, which is output after the row address RA, of the display address MA is the remainder of the address input to the first register 120A among the addresses FA output from the address pipeo 22. The output address of the second register 120B, which stores and outputs an 8-bit address, is input to the second exclusive oracle EX2 and, if it matches, outputs '0' as the output value P3.

The output values P1 and P3 of the first and second exclusive O gates EX1 and EX2 are simultaneously input to the first O gate OR1, and the reference signal is the first flip-flop 131. After latching the row address RA, which is inputted to the Rx, the row address strobe signal RAS is delayed by one clock at the second flip-flop 132. That is, when the output values P1 (P3) of the first and second exclusive OA gates EX1 and EX2 are both '0' and the first address delayed row address strobe signal RAS is '0', The output value COM1 of the first or gate OR1 is maintained at '0' to activate the data write operation by the CPU.

The output value COM1 of the first oragate OR1 is input to the data register 110 to enable the data FD input from the data pipo 21 to be output to the memory control and interface unit 30. Used as a signal.

In addition, the output value COM1 of the first oragate OR1 is input to the control signal generator 140 to generate various control signals for data writing to the video memory 1.

That is, the output value COM1 of the first oragate OR1 is input to the mux 141 for inputting a read or write signal RS (WS) input from the memory control and interface unit 30, and the output value COM1 of the first oragate OR1. If COM1 is '0', the output signal is output as the write signal WS, and if '1' is output as the read signal RS, the data MD output from the data register 110 is recorded in the video memory 1. Be sure to

In addition, the output value COM1 of the first oragate OR1 and the column address strobe signal CAS output from the VGA graphics controller 40 are combined at the second oracle OR2 through the AND gate AND1. The data pipo read signal FR is output.

The PIPO read signal FR may include the respective PIPO 21 in a state where the register 120 and the data register 110 are empty, that is, when the data PIPO 21 and the address PIPO 22 are empty. 22 is a signal for automatically reading the data FD and the address FA from the register 120 and the data register 110 until all the data FD and the address FA are stored. .

That is, when the PIPO recording signal FW and the PIPO empty signal by the CPU are input to the third or gate OR3, the output values are input to the third flip-flop 142 and the fourth flip-flop 143. The clock is delayed by two clocks, and the first state is continuously maintained. At the same time, the PIPO recording signal FW is input to the fifth flip-flop 144 to delay the clock and output the output value at the inverting stage.

Then, the output value of the fifth flip-flop 144 is input to the fourth or gate OR4 together with the output value of the fourth flip-flop 143, and then the output value of the fourth orifice OR4 is made to the fourth value. The six flip-flop 145 is input to the AND gate AND1 together with the output value of the second oracle OR2.

At this time, the output value of the AND gate AND1 is '0 (negative pulse)' when the write signal FW and the PIFF empty signal are input to the third orifice OR3. Alternatively, when the output value COM1 of the comparator 130 input to the control signal generator 140 and the column address strobe signal CAS of the display address MA output from the VGA graphics controller 40 are simultaneously '0'. '0' is output. This output value outputs the PIPO read signal FR, and the data FD and the address FA recorded in each PIPO 21 and 22 are input to the data register 110 and the register 120, respectively. . As a result, the data register 110 and the register 120 continue to input until the data FD and the address FA stored in the respective PIPO 21 and 22 become empty. During the above operation, each PIPO 21 or 22 becomes empty and data and address are inputted again from the CPU, and the PIPO read signal FW by the write signal FW and the PIPO empty signal by the CPU. ) Is output.

As described above, according to the present invention, an address comparison and control signal generation unit for comparing the data to be recorded from the CPU to the video memory, the PIPO storing the address, and the address of the data to be displayed and the address of the data to be recorded. This makes it possible to display data simultaneously with the data recorded by the CPU, which eliminates the need for data recording time to the video memory, and also allows the CPU to record data in the video memory by writing to an internal PIPO during data recording by the CPU. The shorter time reduces the load on the CPU, thereby improving the performance of the graphics system's display and data writing operations, making it very effective.

Claims (2)

In constructing a graphics system for recording or reading and displaying video data into video memory under the control of the CPU, a bus interface unit 10 for interfacing data and control signals from the CPU via ISA, EIAS and local buses and ; A clock generator 90 generating a reference clock of the system; A drawing coprocessor (20) for temporarily storing data (SD) input from the bus interface unit (10) or processing data in the video memory (1); A data piepo 21 and an address piepo 22 for storing data and an address by the CPU input from the drawing coprocessor 20, respectively; A memory control and interface unit 30 for accessing (reading / writing) data stored in the video memory 1; It consists of general purpose register, sequence register, and graphic control register, and stores the data (SD) in various registers through the various interface units 10 to manage mode control, characteristic control, memory mode, graphics map clock mode, and the like. A controller 40; CRTC for controlling a cathode ray tube by storing information about a resolution corresponding to a mode selected by the VGA graphics controller 40 to count a video clock output from the clock generator 90 to generate a reference timing of the displayed data. 50); Inputting the display data MD of the video memory 1 input through the memory control and interface unit 30 and combining the VGA attributes thereof to output the pixel data PD according to the timing of the CRTC 50. A display control unit 60; A hardware cursor (70) for indicating, as a cursor, a position at which display data (MD) is to be displayed from the memory control and interface section (30); A DAC (80) for inputting digital pixel data (PD) from the display control unit (60), converting it into an analog signal, and outputting various color signals (R, G, B); The address FA stored in the data pipeo 21 and the address pipeo 22, respectively, and the address of the data to be accessed and displayed by the VGA graphics control unit 40 are compared and the data pipeo according to the match. And an address comparison and control signal generation unit 100 for displaying the data FD stored in the 21 in the video memory 1 while simultaneously displaying the data FD stored in the memory control and interface unit 30. Graphics acceleration system. The register of claim 1, wherein the address comparison and control signal generation unit (100) inputs an address (FA) from an address pipe (22) that stores a corresponding address (SA) of data (SD) by a CPU. 120; The display address MA and its row address strobe signal RAS are inputted from the VGA graphics control unit 40 to display the display address MA and the address FA by the register 120. A comparison unit 130 for comparing and outputting a signal according to whether there is a match; The video is enabled according to the output signal COM1 of the comparator 130 so that the data FD input from the data pipeo 21 is displayed on the monitor screen through the memory control and interface unit 30. A data register 110 for writing to the memory 1; Read output from the memory control and interface unit 30 so that the data MD output from the data register 110 can be recorded in the video memory 1 according to the output signal COM1 of the comparator 130. While converting the signal RS into the recording signal WS, the output signal COM1 of the comparator 130 and the column address strobe signal CAS of the display address MA output from the VGA graphics controller 40 are converted. When a PIPO write signal is input by the CPU in an initial state in which no data is input to the register 120 and the data register 110, the data and address pi is input to the register 120 and the data register 110. And a control signal generator (140) for outputting a PIPO read signal (FR) so that the data (FD) and the address (FA) of the fabric (21) (22) are input.