JP2917659B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a write buffer, and more particularly, to an information processing apparatus for speeding up processing when it is desired to maintain consistency between a write buffer and a memory.

[0002]

2. Description of the Related Art Conventionally, as an information processing apparatus, as shown in FIG. 2, a CPU unit 6 comprising a CPU 3, a cache 4, and a read / write buffer 5, a register group 7, a memory 8 and an I / O 9 are connected by a bus 2. There is something connected.

In this information processing apparatus, as a dummy read method for emptying a write buffer , non-capacity is used.
There is a way to perform flash access. This non-cached
For access, the line must be
You have to wait until the buffer is empty. did
Therefore, when it is necessary to complete the write operation from the CPU, such as displaying the status of the system and synchronizing with the external interface, a dummy read is performed on the memory or the register in the non-cache area to ensure consistency with the memory. , The write buffer was empty.

A dummy read to a non-cache area for emptying the write buffer has been accessed along a path shown by a dotted line in FIG. This took several clocks.

[0005]

However, in the above-mentioned information processing apparatus, the memory or the register has a speed limitation, and the result is not necessary because the data is merely a dummy read. There is a drawback that you have to wait until the result comes even after you have become.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an information processing apparatus capable of performing high-speed dummy reading for emptying a write buffer.

[0007]

In order to attain the above object, an information processing apparatus according to the present invention comprises a CPU unit comprising a CPU, a cache and a write buffer, a register group, a memory and an I / O connected by a bus. When it is necessary to complete a write operation from the CPU, such as displaying a system status or synchronizing with an external interface, at the time of bus reading, an information processing unit having a means for emptying the write buffer in order to ensure consistency between the write buffer and the memory. equipment to
In this case, a high-speed dummy register for performing high-speed dummy reading for emptying the write buffer is provided on the bus.

[0008]

According to the information processing apparatus having the above-described configuration, by providing a high-speed register for a dummy read on a bus, the waiting time during a dummy read can be reduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an information processing apparatus according to an embodiment of the present invention equipped with a dummy read high-speed register.

Referring to FIG. 1, reference numeral 6 denotes a CPU unit,
It comprises a PU 3, a cache 4, and a read / write buffer 5. The CPU unit 6 is provided with a register group 7,
It is connected to the main memory 8 and I / O 9.

This information processing apparatus is also required to complete the write operation from the CPU 3, such as displaying the system status and synchronizing with the external interface, at the time of reading the CP bus. To empty the write buffer 5 in order to obtain

Reference numeral 1 denotes a high-speed register for dummy reading provided on the bus 2 for performing high-speed dummy reading for emptying the write buffer 5 and accessed by the CPU 3. Where the dummy
The high-speed read register 1 is different from the normal register group.
No action is taken. For example, the usual
The register returns the value held in the register when reading,
There are actions such as
There is no. Therefore, by accessing the bus,
Read the normal register when you want to empty the buffer
If the write buffer is emptied,
The contents of the dummy register are returned.
Time can be saved.

As described above, according to the information processing apparatus of this embodiment, the access to the non-cache area for completing the write operation of the CPU is as shown by the dotted line in FIG. A read instruction issued from CPU 1 to register 1 goes out to bus 2 without accessing cache 4,
Before that, the write buffer 5 must be empty. When the write buffer becomes empty, a read instruction is issued on the bus 2, and the register 1 terminates processing immediately upon receiving the instruction.

That is, when it is necessary to complete the write operation from the CPU, and when dummy reading a memory or register on the bus to empty the write buffer,
The CPU 3 accesses the high-speed register for dummy read 1 via the bus 2.

As a result, conventionally, the register 7 and the memory 8
However, these operations take a long time because they have to wait for the operation to be completed and a result to be returned even though they are dummy reads. On the other hand, the high-speed register 1 of this embodiment terminates its operation immediately after receiving the instruction, so that the processing can be performed in a short time.

[0016]

As described above, according to the information processing apparatus of the present invention, a high-speed register that can be accessed as a non-cache area is provided on a bus, so that the write buffer and the memory can be consistent. This has the effect that the dummy read for emptying can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an information processing apparatus according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High speed register for dummy read 2 Memory bus 3 CPU 4 Cache 5 Read / write buffer 6 CPU part 7 Register group 8 Memory 9 I / O

Claims (1)

(57) [Claims] 1. A CPU comprising a CPU, a cache and a write buffer, a register group, a memory and an I / O
O is connected by a bus, and the system status is displayed when the CP bus is read, and the CPU is synchronized with the external interface.
When it is necessary to complete the write operation from, Oite the information processing apparatus having the emptying means a write buffer for consistency of the write buffer and memory, the dummy leads for the write buffer empty A high-speed dummy register for performing high-speed processing is provided on a bus.