JPH0512120A - Data cache control system - Google Patents

Abstract

PURPOSE:To shorten the stop time of a processor due to the updating of a cache memory. CONSTITUTION:A cache updating address monitoring means 23 collating with the contents of an addition means 24 and an address register 22 and notifying a common control means 21 of the result when the data requested by the processor 1 is read-in, is provided. When a cache is updated due to the mistake in making access to the data cache, by permitting the continuation of the processor when the data required for the processor are read in, storing the residual part in a buffer and performing the updating in the idle time of a cache bus, the stop time of the processor can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to a data cache memory control system.

[0002]

2. Description of the Related Art An example of a device using a conventional data cache is shown in FIG. 2, and a time chart of an operation example according to FIG. 2 is shown in FIG.

In the conventional cache system shown in FIG. 2, if the requested data from the processor 1 is not present in the cache memory 4, the common control means 21 reads the data of the cache update unit from the storage device 3 and buffers the read data. It is read into the means 28, and at the same time, the address adding means 24
The data memory 41 of the cache memory 4
Also, the contents of the tag memory 42 are updated, and after the cache is updated, the processing execution of the processor is permitted.

In the figure, 2 is a data cache control means, 22 is an address register, 25 is an address selecting means, 251 is a cache address bus, 26 is a cache tag collating means, 27 is a cache data driver, 2
Reference numeral 9 is a write data buffering means.

Reference numeral 411 denotes a cache data bus, 4
21 is a tag bus, 51 and 52 are address buses, 61 and 6
Reference numeral 2 is a data bus, and 7 is a processor control signal.

[0006]

In the above-mentioned conventional technique, even after the requested data is read from the storage device 3, the processing execution of the processor 1 is stopped until the entire update unit is written in the cache memory 4. There's a problem. In particular, the influence is great in a device in which data exists in a dispersed manner.

An object of the present invention is to provide a data cache control system that solves the above problems.

[0008]

In order to achieve the above object, in the data cache control system according to the present invention, a processor for processing by a command and data supplied from a storage device and a plurality of storage units are combined into one. An update unit, a normal cache memory for supplying data to this processor at high speed, a storage device for storing data to be supplied to the processor and the cache memory, and a processor, a cache memory and a storage device connected to the storage device. , An address register holding the address of the data request from the processor, a means for outputting the address to the storage device for updating the contents of the cache memory, and writing the data read from the storage device to the corresponding address of the cache memory Means for adding addresses for this purpose, and this address adding means A connected and added address, a means for comparing and monitoring the address in the address register, a means for connecting one of the address adding means and the address register, and selecting one of the addresses output from both means, A read data buffering means for temporarily holding the data read from the storage device, a write data buffering means for temporarily holding the data written out from the processor, and absorbing the speed difference between the storage device and the processor, By supplying the necessary timing signals to the above means, outputting a stop request signal for updating the cache to the processor, and receiving a data request signal from the processor, the cache is updated. It has a common control means that has the function of interrupting the operation, and the data requested by the processor when updating the cache. From the time the read permits the processing continue processor, using no processor data request time, it is to update the rest of the cache.

[0009]

According to the present invention, when the cache is updated due to an access miss in the data cache, the processor is allowed to continue processing when the data required by the processor is read, and the remaining portion is held in the buffer so that the cache By updating the bus during free time, the processor stop time is shortened.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, the cache structure of the direct map method is shown for simplicity, but it is obvious that the same effect can be obtained with other methods.

In FIG. 1, in this embodiment, the storage device 3
Processor 1 for processing by instructions and data supplied from the processor 1, a normal cache memory 4 for supplying data to this processor at high speed with a plurality of storage units as one update unit, processor 1 and cache memory 4
To the processor 3, the cache memory 4, and the storage device 3 for storing the data supplied to the processor 1, the address register 22 for holding the address of the data request from the processor 1, and the update of the contents of the cache memory 4. Connected to the address adding means 24, a means for outputting an address to the storage device 3, a means 24 for adding an address for writing the data read from the storage device 3 into a corresponding address of the cache memory 4, and an address adding means 24. , An address selection unit connected to the update address monitoring unit 23 for comparing and monitoring the added address and the address in the address register 22, and the address addition unit 24 and the address register 22, and selecting one of the addresses output from both units. Means 25 and reading for temporarily holding the data read from the storage device 3. Only the data buffer means 28, the write data buffer means 29 for temporarily holding the data written from the processor 1 and absorbing the speed difference between the storage device 3 and the processor 1, and the above-mentioned means. Is supplied to the processor 1, and a stop request signal for updating the cache is output to the processor 1.
Common control means 21 having the function of interrupting the cache update operation by receiving a data request signal from
Have and.

When updating the cache, the processor 1 is allowed to continue processing from the time when the data requested by the processor 1 is read, and the remaining cache is updated using the time when the processor 1 does not request the data.

Further, 2 is a data cache control means, 4
Reference numeral 1 is a data memory, and 42 is a tag memory.

The processor 1 is supposed to be supplied with instructions by other means. When the processor 1 requests data, the address of the requested data is output to the address bus 51. Address register 2 of data cache control means 2
2, the address is held, the contents of the tag memory 42 on the cache memory 4 and the contents of the address register 22 are collated by the cache tag collating means 26, and if valid data exists in the cache memory 4, the data memory 4
The data read by the cache data bus 411 from 1 is returned to the processor 1 via the data bus 61.

If valid data does not exist in the cache memory 4 as a result of the collation by the cache tag collating means 26, the common control means 21 causes the processor control signal 7 to
The processor 1 is instructed to stop the processing for reading the data, and the address bus 52, the data bus 62, and the control bus 211 read the update unit data from the storage device 3 into the buffer unit 28. At the same time, the buffer adding means 24 adds the buffer adding means 24 to the corresponding address of the cache memory 4
The contents of 8 are sequentially written.

At this time, the cache update address monitoring means 23 collates the contents of the adding means 24 and the address register 22 and notifies the common control means 21 at the time when the requested data of the processor is read.

In response to this notification, the common control means 21 outputs the request data from the buffer means 28 to the processor 1 via the data bus 61. At the same time, processor control signal 7
Allows the processor 1 to execute processing, and the processor 1
Restarts processing.

After that, the common control means 21 updates the contents of the address addition means 24 while updating the contents of the cache memory 4.
Is updated for all update units. When a data request is generated from the processor 1 while the cache memory 4 is being updated, the common control means 21 is notified by the data request instruction signal 8 and the common control means 21 keeps The update operation of the cache memory is interrupted, and the cache control means 2 performs a normal data supply operation.

[0020]

As described above, in the data cache control means of the present invention, the processing of the processor can be restarted even during the updating.

The effects of the present invention will be described with reference to the time charts of FIGS. FIG. 3 shows an example using the data cache of the present invention, and FIG. 4 shows an example using the conventional data cache.

In this example, the cache update unit is 4 addresses, and the storage device calling time is 2 clocks.

In the processing of # 1, this is an example of the case where data is requested and is not in the cache. The request data is assumed to be located at the third position among the four update unit addresses. In FIG. 3 of the present invention, request data can be received at the fifth clock after the processor is stopped, and thereafter, # 2 and # 3 can be continuously executed. In FIG. 4 according to the conventional technique, the processor is in a stopped state for 6 clocks until the update is completed, and then the process is restarted.

In this way, it is possible to shorten the processor stop time when there is no requested data in the data cache.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a timing chart according to the embodiment of FIG.

FIG. 4 is a timing chart according to the conventional example of FIG.

[Explanation of symbols]

 1 processor 2 data cache control means 3 storage device 4 cache memory 7 processor control signal 8 data request instruction signal 21 common control means 22 address register 23 update address monitoring means 24 address adding means 25 address selecting means 26 cache tag matching means 27 cache data Driver 28 Read data buffering means 29 Write data buffering means 41 Data memory 42 Tag memory 51,52 Address bus 61,62 Data bus 251 Cache address bus 411 Cache data bus 421 Tag bus

Claims (1)

Claim: What is claimed is: 1. A processor for performing processing according to instructions and data supplied from a storage device, and a plurality of storage units as one update unit, which is an ordinary unit for supplying data at high speed to the processor. Cache memory, a storage device that stores data to be supplied to the processor and the cache memory, an address register that is connected to the processor and the cache memory and the storage device, and holds an address of a data request from the processor, and a cache. A means for outputting an address to the storage device for updating the contents of the memory, a means for adding the address for writing the data read from the storage device to the corresponding address of the cache memory, and a device connected to this address addition means , The added address and the address in the address register Means for comparing and monitoring, means for selecting one of the addresses output from both means, connected to the above-mentioned address adding means and the above-mentioned address register, and read data for temporarily holding the data read from the storage device. The buffer means, the buffer means for temporarily storing the data written from the processor, and the buffer means for absorbing the write data for absorbing the speed difference between the storage device and the processor, and supplying the necessary timing signal to each of the above means. , A common control unit having a function of outputting a stop request signal for updating the cache to the processor and receiving a data request signal from the processor to interrupt the cache update operation, When updating the cache, the processor is allowed to continue processing from the point when the data requested by the processor is read, and the processor Using no data request time, the data cache control method and updates the remaining cache.