JPH0816390A - Microprocessor - Google Patents

Abstract

PURPOSE:To execute a program without any contradiction by matching the contents of cache memories for instruction and for data by writing the same data into the cache memory for instruction in the case where write access to the cache memory for data occurs. CONSTITUTION:When a flag showing whether operating a deciding circuit or not is turned on and the write access to a cache 3 for data occurs, the deciding circuit decides whether an entry corresponding to a write address is stored in a cache 5 for instruction or not. As a result, when that entry is stored, a write control circuit 1 writes the write data into the correspondent entry of the cache 5 for instruction. When that entry is not stored, the write control circuit 1 does nothing. When the flag showing whether operating the deciding circuit or not is turned off, the deciding circuit is not operated and the write control circuit 1 does not do anything, either even when the write access to the cache 3 for data occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having an instruction cache memory and a data cache memory independently, and more particularly to a microprocessor having an architecture which allows rewriting of instructions.

[0002]

2. Description of the Related Art As a conventional technique, Japanese Patent Laid-Open No. 63-364
As described in "Rewriting Method of Preceding Read Command" in Japanese Patent Publication No. 41, when rewriting an instruction, it is known that the rewriting instruction can be written also in the preceding read register.

[0003]

In recent years, an increasing number of microprocessors have an instruction cache memory and a data cache memory independently in order to improve the cache hit rate. In this case, an instruction that prohibits the rewriting of instructions, as is found in general RISC processors, is used.
There is no problem with the architecture, but the conventional C
For an architecture that allows rewriting of instructions as seen in the ISC processor, the contents of the instruction cache memory and the data cache memory must always match.

Considering an architecture microprocessor which has an instruction cache memory and a data cache memory independently, and which allows rewriting of instructions, the above prior art is read in advance. Although the instruction rewriting is considered for the instruction, it is not considered that the contents of the instruction cache memory and the data cache memory are always matched.

A first object of the present invention is to execute instruction rewriting in an microprocessor having an architecture which has an instruction cache memory and a data cache memory independently and allows instruction rewriting. In this case, the contents of the instruction cache memory and the data cache memory are always matched to provide a microprocessor in which a program can be executed without contradiction.

A second object of the present invention is clear even in the case of an architecture microprocessor which has an instruction cache memory and a data cache memory independently of each other and permits instruction rewriting. For a program in which instructions are not rewritten, unnecessary microprocessor cache memory is not rewritten, and a microprocessor is provided that allows programs to be executed efficiently.

[0007]

The first object of the present invention is to:
When a write access to the data cache memory occurs, it is achieved by writing the same data to the instruction cache memory. That is, the instruction cache memory determines whether or not the entry corresponding to the write access address to the data cache memory is stored, and according to the output of the determination circuit,
This is achieved by providing a write control circuit for writing write data to the corresponding entry of the instruction cache memory. A second object of the present invention is to provide a flag indicating whether or not to operate the judgment circuit, and when the flag is on, operate the judgment circuit to write to the instruction cache memory, and When the flag is off, nothing is done in the instruction cache memory for the write access.

[0008]

According to the present invention, the instruction rewriting is executed in the microprocessor of the architecture which has the instruction cache memory and the data cache memory independently and permits the instruction rewriting. Even if
The contents of the instruction cache memory and the data cache memory can always be matched, and the program can be executed without contradiction.

That is, when a write access to the data cache memory occurs when the flag indicating whether or not to operate the determination circuit is on, the determination circuit causes the entry corresponding to the write address. However, it is determined whether or not it is stored in the instruction cache memory. As a result, if it is stored, the write control circuit writes the write data to the corresponding entry of the instruction cache memory. If not stored, the write control circuit does nothing.

On the other hand, when the flag indicating whether or not to operate the judgment circuit is in the off state, the judgment circuit does not operate and the write operation is performed even if a write access to the data cache memory occurs. The control circuit does nothing. The present invention operates as described above and does not malfunction.

The present invention can be implemented without depending on the cache implementation method described above. That is, the cache method may be the write-through method or the write-back method. The direct mapping method or the n-way set associative method may be used.

[0012]

EXAMPLES An example of the present invention will be described below.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 1 is an instruction cache write control circuit, 2 is an instruction cache hit determination circuit associated with data write, 3 is a data cache, 4 is a data address array, 5 is an instruction cache, and 6 is A 2-port instruction address array, 7 is a data cache control circuit,
8 is an instruction cache control circuit, 9 is a data cache hit determination circuit, 10 is an instruction cache hit determination circuit, and 11 is a register for holding data read from the data cache (see FIG. Medium, MBR (Memory
(Buffer Register)), 12
Is a register for holding an address for accessing the data cache (in the figure, D-MA (Data Mem)
and 15 is a register for holding an address for accessing the instruction cache (I-MA (Inst in the figure).
reduction Memory Address Re
13) is a flag for deciding the operation / non-operation of the hit determination circuit 2 of the instruction cache associated with the data write, and 14 is a register (MBW (Memory B in the figure) for holding the write data for the cache).
16 is a register for holding an instruction read from the instruction cache 5 (IR (Instructio in the figure).
n Register)), 17 is an instruction execution control circuit for controlling the execution of the instruction read from the instruction cache 5.

First, the procedure for reading the instruction cache 5 will be described. The instruction execution control circuit 17 sends a read request signal 104 to the instruction cache 5 to the instruction cache control circuit 8 and also the I-MA1.
5, the access address 122 of the instruction cache 5 is set. The instruction cache control circuit 8 uses the I-MA1
The instruction address array 6 is read using the access address 122 of the instruction cache 5 set to 5. At this time, the address selector 120 has the selector control signal 107 sent from the instruction cache write control circuit 1.
Selects the access address 122 of the instruction cache. The tag data read from the instruction address array 6 is compared with the access address 122 of the instruction cache 5 in the hit determination circuit 10 of the instruction cache 5, and the result is a hit signal 113 as the instruction cache control circuit 8 Be transmitted to. If the information of the hit signal 113 is a hit, the instruction cache control circuit 8 sends a response signal 105 to the instruction execution control circuit 17, and the instruction execution control circuit 17 outputs the instruction read from the instruction cache 5. Set to IR16. The instruction set in the IR 16 is transmitted to the instruction execution control circuit 17 and executed. If the information in the hit signal 113 is not a hit, the instruction cache control circuit 8 issues an access request (not shown) to the secondary cache or the main storage device, and outputs desired data to the bus 117 and the instruction. Cache 5
And IR16, the response signal 105 is sent to the instruction execution control circuit 17.

Next, the procedure for reading the data cache 3 will be described. The instruction execution control circuit 17 sends a read request signal 101 to the data cache 3 to the data cache control circuit 7 and, at the same time, D-
Access address 1 of data cache 3 in MA 12
Set 21. The data cache control circuit 7
Data cache 3 set in D-MA12
The tag data is read from the data address array 4 using the access address 121. The tag data read from the data address array 4 is compared with the access address 121 of the data cache 3 in the hit determination circuit 9 of the data cache 3, and the result is a hit signal 112. It is transmitted to the data cache control circuit 7. If the information of the hit signal 112 is a hit, the data cache control circuit 7 sends a response signal 103 to the instruction execution control circuit 17, and the instruction execution control circuit 17 thereby receives the data from the data cache 3. The read data is set in the MBR 11. MBR11
The data set in (1) is transmitted to the instruction execution control circuit 17 and used. If the information of the hit signal 112 is not a hit, the cache control circuit 7 issues an access request (not shown) to the secondary cache or the main storage device, and outputs desired data to the bus 117 and the data cache. 3 and the MBR 11, the response signal 103 is sent to the instruction execution control circuit 17.

Further, the procedure for writing to the data cache 3 will be described. The instruction execution control circuit 17 sends a write request signal 102 for the data cache 3 to the data cache control circuit 7, and at the same time D-
Access address 1 of data cache 3 in MA 12
21 is set, and write data is set in the MBR 11. The data cache control circuit 7 receives the write request signal 102 and uses the access address 121 of the data cache 3 set in the D-MA 12 to write data.
The address array 4 for data is read. The tag data read from the data address array 4 is compared with the access address 121 of the data cache 3 in the hit determination circuit 9 of the data address array 4, and the comparison result is a hit. A signal 112 is transmitted to the data cache control circuit 7. If the information of the hit signal 112 is a hit, the write enable signal 114 is sent to the data cache 3 and the data set in the MBW 14 is written. On the other hand, on the instruction cache side, the instruction cache write control circuit 1 monitors the write request signal 102 for the data cache 3 sent from the instruction execution control circuit 17, and when the write request signal 102 is output, the data is written. Access address 12 of data cache 3
1 reads out the instruction address array 6. The tag data read from the instruction address array 6 is compared with the access address 121 of the data cache in the hit determining circuit 2 of the instruction cache, and the result is hit signal 111 to the instruction cache write control circuit 1. Be transmitted to. In the instruction cache write control circuit 1,
If the flag 13 for deciding the operation / non-operation of the instruction cache hit determination circuit 2 associated with the write is on and the information of the hit signal 111 is a hit, a write request signal to the instruction cache control circuit 8 is issued. 106 is sent out. The instruction cache control circuit 8 sends a write enable signal 115 to the instruction cache 5 to write the data set in the MBW 14. At this time, in the address selector 120, the selector control signal 107 sent from the instruction cache write control circuit 1
Access address 121 of data cache 3
Is output selectively. In the instruction cache write control circuit 1, if the flag 13 that determines the operation / non-operation of the hit determination circuit 2 of the instruction cache 5 associated with the data write is in the off state, or if the information of the hit signal 111 does not hit. ,do nothing.

When the instruction cache write control circuit 1 finishes monitoring the data write, it sends a monitoring end signal 108 to the data cache control circuit 7, and the cache control circuit 7 receives the instruction. The response signal 103 is sent to the execution control circuit 17, and the write access ends.

Further, a flag 13 for deciding the operation / non-operation of the hit decision circuit 2 of the instruction cache associated with the data write.
Is set / reset by software instruction using a dedicated instruction.

As described above, the data can be written to the instruction cache 5 and the program can be executed without contradiction.

According to the above embodiment, the instruction cache memory and the data cache memory are independently provided, and
Even if an instruction is rewritten in an architecture microprocessor that allows instruction rewriting, the contents of the instruction cache memory and the data cache memory are always matched to execute the program without contradiction. be able to.

Further, even in the case of an architecture microprocessor which has an instruction cache memory and a data cache memory independently and permits instruction rewriting, it is obvious that the instruction rewriting is not performed. With respect to such a program, the function of the flag 13 can eliminate unnecessary rewriting of the instruction cache memory and can efficiently execute the program.

[0022]

According to the present invention, the instruction rewriting is executed in the microprocessor of the architecture which has the instruction cache memory and the data cache memory independently and permits the instruction rewriting. Even if
The contents of the instruction cache memory and the data cache memory can always be matched so that the program can be executed without contradiction.

According to the present invention, the instruction cache memory and the data cache memory are independently provided, and even if the microprocessor has an architecture that allows the rewriting of instructions, the instructions are obviously provided. For a program that is not rewritten, the unnecessary rewriting of the instruction cache memory can be eliminated and the program can be efficiently executed.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

1 ... Instruction cache writing control circuit, 2 ... Hit determination circuit, 3 ... Data cache, 4 ... Data address array, 5 ... Instruction cache, 6 ... 2-port instruction address array, 7 ... Cache control circuit for data, 8 ...
Instruction cache control circuit, 9 ... Data cache hit determination circuit, 10 ... Instruction cache hit determination circuit, 11 ... Register (MBR) for holding data read from the data cache, 12 ... A register (D-MA) for holding an address for accessing the data cache, 13 ... A flag for determining the operation / non-operation of the instruction cache hit determination circuit 2 associated with the data write, 14 ... A write data for the cache -A register holding the data (MBW), 15 ... A register holding the address for accessing the instruction cache (IM
A), 16 ... A register (IR) for holding the instruction read from the instruction cache, 17 ... An instruction execution control circuit for controlling the execution of the instruction read from the instruction cache.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Murashima 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Hitachi Ltd. Office Systems Division (72) Inventor Toshiro Akiyama 10-22 Sakae, Naka-ku, Nagoya-shi, Aichi No.Nitori Chubu Software Co., Ltd.

Claims (1)

[Claims] 1. A microprocessor having an instruction cache memory and a data cache memory independently, wherein when a write access to the data cache memory occurs, the instruction cache memory is written to the data cache memory. A judgment circuit for judging whether or not there is an entry corresponding to the write access address to the data cache memory, and when the judgment circuit judges that the entry exists, the write data to the data cache memory is written. A microprocessor provided with a write control circuit for writing the data into a corresponding entry of the instruction cache memory, and a flag indicating whether or not to operate the determination circuit.