JPH0498352A - Buffer invalidation control system - Google Patents

Abstract

PURPOSE:To make the maximum use of high speed and to improve the performance of a whole system by controlling a system in such a way that a buffer invalidating request command is ignored when the command from the other cache memory for the same area is detected in a prescribed period. CONSTITUTION:When write requests into the same internal area are simultaneously generated in cache memories 1A and 1B, they function to ignore the command concerned when they detect the buffer invalidating request command from the other cache memories 1B and 1A for the same area within the prescribed time after they transmit the buffer invalidating request command by a buffer invalidating request command transmission means P1 to a system bus. Thus, the same area in the other cache memory can be invalidated without erasing rewritten data and coincidence control with a common memory 3 can be realized. Thus, the merit of a copy back system (high speed processing) can be made the best use of and the performance of the system can be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a technology for controlling buffer invalidation processing between multiple copy-back type cache memories, without erasing the rewritten portion in the cache memory.
The aim is to take full advantage of the high speed that is the advantage of the copy-back method and ultimately contribute to improving the performance of the entire system. Each cache memory has an address field, a data field, and a valid indication flag in each internal entry. and a changed instruction flag, and when there is a data write request from the corresponding CPU, if the target area is registered in the cache memory and the changed instruction flag is off, the CPU means for sending a buffer invalidation request command including at least a portion of a write address from another cache memory to the system bus; means for erasing the address area included in the command from within its own cache memory when the command is in question, register means for holding the address of the buffer invalidation request command sent by itself, and buffer invalidation from the other cache memory. means for comparing the address included in the request command with the contents of the register means, and a buffer invalidation request command is sent from another cache memory to the same area within a certain period of time after sending the buffer invalidation request command. If a command is detected, the command is configured to be ignored.

[Industrial application field]

The present invention relates to a multiprocessor system in which a plurality of copy-back type cache memories and at least one shared memory are connected via a system bus,
In particular, the present invention relates to a technique for controlling buffer invalidation processing for invalidating the same area in other cache memories when write requests occur simultaneously to the same area in each cache memory.

[Conventional technology]

An example of a conventional cache memory control mode is shown in FIGS. 6(a) to 6(C).

In the illustrated example, both cache memories A and B are
It is assumed that this is a back-type cache memory. Further, ■ indicates a valid instruction flag indicating whether or not the area specified by the access address exists in the own cache memory, and M indicates a changed instruction flag indicating whether or not the data has been rewritten.

(Refer to FIG. 6(a)) In each of cache memories A and B, when there is a data write request from the corresponding CPU, the target area is registered in its own memory (V- 1) When the changed instruction flag M is off (M=O), the write data is written to the target area (entry), and the changed instruction flag M is turned on (M=1).

In the illustrated example, when cache memory A writes data to an unmodified area, it sends a buffer invalidation request command to the system (→■).

Cache memory B is trying to send a buffer invalidation request command in the same way as cache memory A, but because cache memory A happens to operate faster, it cannot acquire the right to use the system bus, and the buffer invalidation request is sent. The system enters a command sending wait state (=:) ■).

(See FIG. 6(b)) In response to the buffer invalidation request command from cache memory A, cache memory B enters a store wait state for storing data in the same area into shared memory C. Furthermore, cache memory A has finished sending the buffer invalidation request command from its own memory, so cache memory A
It accepts write requests from the PU and returns a write completion response.

Since the buffer invalidation request command has been sent from cache memory A to the same area as the buffer invalidation request command that is in the sending waiting state, cache memory B tries to cancel the sending waiting state. As shown in the operation timing of FIG. 7, the cancellation cannot be executed.

Therefore, the buffer invalidation request command that has been waiting to be sent in cache memory B is sent onto the system bus (→■).

(See FIG. 6(c)) Cache memory B stores the data in the store waiting state to shared memory C (=+■).

On the other hand, in cache memory A, the same area is cleared by the buffer invalidation request command sent from cache memory B, and therefore data is lost.

[Problem to be solved by the invention]

In the conventional control method described above, when write requests occur simultaneously to the same area of multiple copy-back cache memories (two cache memories in the 6th example), buffer invalidation is disabled from both cache memories. There is a disadvantage that the conversion request command is sent onto the system bus. In other words, as shown in the operation timing diagram of FIG. 7, immediately after detecting a buffer invalidation request command from another cache memory, the transmission of the buffer invalidation request command from the own cache memory cannot be canceled in time. Therefore, there is an inconvenience that buffer invalidation request commands are sent from both cache memories, and both write data are lost.

In order to avoid this inconvenience, countermeasures can be considered, such as allowing only one CPU to rewrite the shared area through software control (copy-on-write method), but this is extremely complicated to control. I can't say it's practical.

Another method is to simultaneously write the data in the target area to the shared memory C at the step (■) above, but this method has the advantages of the copy-back method (reducing the frequency of bus access, high-speed processing). Therefore, the problem arises that the performance of the entire system deteriorates.

The present invention was created in view of the problems in the prior art, and it takes full advantage of the high speed that is the advantage of the copy-back method without erasing the rewritten portion in the cache memory, and ultimately improves the efficiency of the entire system. The purpose of this invention is to provide a buffer invalidation control method that can contribute to improved performance.

[Means to solve the problem]

As shown in the principle diagrams in Figures 1(a) and (b),
The buffer invalidation control method of the present invention includes a plurality of copy-back type cache memories M1 to Mn and at least one
In a multiprocessor system in which two shared memories CM are connected via a system bus, each cache memory Mi has an address section A, a data section D, and an area indicated by an access address in each internal entry as its own cache. It has a valid indication flag ■ indicating whether the data exists in the memory or not, and a changed indication flag M indicating whether the data has been rewritten,
In addition, when there is a data write request from the corresponding CPU, if the target area is registered in the cache memory and the changed instruction flag is off, at least a part of the write address from 1 CPU is included. means P for sending a buffer invalidation request command to the system bus;
means P2 for monitoring a command on the system bus and erasing an address area included in the command from its own cache memory if the command is a buffer invalidation request command from another cache memory; , comprising register means P3 for holding the address of the buffer invalidation request command sent by itself, and means P4 for comparing the address included in the buffer invalidation request command from the other cache memory with the contents of the register means. However, if a buffer invalidation request command from another cache memory for the same area is detected within a certain period of time after sending the buffer invalidation request command, the command is controlled to be ignored.

[Effect]

When each cache memory writes data to an unmodified area based on a write request from the corresponding CPU, it sends a buffer invalidation request command to the system bus. In this case, if a buffer invalidation request command from another cache memory for the same area is detected within a certain period of time after sending the buffer invalidation request command, control is performed to ignore the command.

In other words, when buffer invalidation request commands are issued consecutively to the same area in a cache memory consisting of a plurality of cache memories, the second and subsequent buffer invalidation request commands are ignored. Therefore, it is possible to achieve consistency control with the shared memory without losing the data in the target area.In addition, it is possible to improve the performance of the entire system by taking full advantage of the advantages of the copy-back method. becomes.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 2 shows the configuration of a tightly coupled multiprocessor system to which the buffer invalidation control method of the present invention is applied.

In this system, a plurality of copy-back type cache memories IA and IB (in this embodiment, only two are shown for simplicity) are connected to at least one shared memory 3 (also shown for simplicity) via a system bus 4. (only one is shown). In addition, each cache memory 14.
18 are connected to central processing units (CPU) 2A and 2B that control supply of address information and data reading and writing to the corresponding cache memories, respectively.

FIG. 3 shows the internal configuration of the cache memory in FIG. 2. Note that the portion surrounded by the broken line is the portion that characterizes the present invention.

In the figure, 31 is a tag section (tag memory), which includes an address section that stores the physical address of access data, and a valid instruction that indicates whether or not the area specified by the access address exists in its own cache memory. Flag ■ and a changed indication flag M that indicates whether the data has been rewritten or not.
have.

In addition, each flag ■, M exhibits ``onj'', that is, ``IJ'' when the respective conditions are affirmed, and ``IJ'' when the respective conditions are denied.
"off" or "0".

32 is a decoder (DEC) that decodes the address ADDI from the corresponding CPU; 33 is a comparison circuit that responds to the address registered in the tag section 31, the address ADOI from the CPU, and the flag V bit; 34 is a decoder (DEC) that decodes the address ADDI from the CPU; An inverter 35 responds to the read/write control signal R/-, an inverter 36 responds to the flag M bit.
is the output of the comparison circuit 33 and the output of the inverter 34 (CPU
AND gate 3 that sets the bit of flag M to set state B (signal MSET) in response to write signal CWRT);
7 is the output of the comparator circuit 33 and the output CW of the inverter 34.
an AND gate responsive to RT and the output of inverter 35;
38 is a store buffer that stores the address 4001 from the corresponding CPU, and 39 is a buffer invalidation control circuit that stores the address (invalidation address) of the buffer invalidation request command supplied from the store buffer 38.
It has a function of creating a buffer invalidation request command and sending it to the system bus 4 in response to the output (invalidation command sending request) WU of the IAD and AND gate 37.

Similarly, 40 is a decoder (DEC) for decoding address ADD2 on system bus 4, and 41 is a decoder (DEC) for decoding address ADD2 on system bus 4;
01) Comparison circuit responsive to bit 2 and flag V, 42
is the invalidation address I supplied from the store buffer 38
A delay buffer 43 that delays AD for a predetermined time compares the output address of the delay buffer with the address ADD2 on the system bus 4 (in this case, the address BIAD of the buffer invalidation request command from another cache memory). 44 is an inverter that responds to the output of the comparator circuit 43, and 45 clears the flag ■ bit in response to the output of the inverter and the output of the comparator circuit 41 (
VCLR) shows an AND gate.

Note that in the comparison circuit 33, the valid instruction flag ■ is on (V=
In the state of 1), when the address of the tag section 31 and CP[J address ADDI match, the output is set to "1", thereby making the corresponding AND gate 36 "valid". If the change method instruction flag M is off (M=O) in this state (the output of the comparison circuit 33 is "do"), the output of the inverter 35 becomes "1" and the AND gate 37 becomes "valid j".

On the other hand, the comparator circuit 43 sets its output to "1" when the address BIAD of the buffer invalidation request command from another cache memory on the system bus 4 matches the invalidation address IAD after a predetermined time delay. The output of the inverter 44 is set to "0" and the AND gate 45 is set to "0".
To disable. In other words, the AND gate 45 becomes "valid" when both addresses IAD and BIAD do not match.

This situation is 1! i (the output of the comparison circuit 43 is "0"), and the comparison circuit 41 detects when the address of the tag section 31 and the address ADD2 on the system bus 4 match with the valid indication flag ■ being on (V-1). The output is set to 1'', thereby clearing the flag ■ bit through the AND gate 45.

Next, a buffer invalidation control method will be described with reference to FIGS. 4(a) to 4(c).

(See Figure 4 (a)) ■ Cache memories 1M and IB are registered in their own memory (V=1) and the change method instruction flag is off (M
= 0) corresponding to the area where C P
When there is a write request from U2A or 2B, the data and address resulting from the write request are held in the target entry and the store buffer 38 (however, the one for data is not shown in FIG. 3), and the corresponding CPU completes the write. At this time, the entry to be rewritten moves from the unchanged state to the changed state, so the cache memory IA,
IB each turns on the change method instruction flag M (M = 1
).

■ Cache memory IA sends a buffer invalidation request command to system bus 4 (write-once operation)
.

■ Cache memory IB sends (issues) a buffer invalidation request command in the same way as cache memory IA.
However, because the cache memory IA happened to operate faster, the right to use the system bus could not be acquired, and the buffer invalidation request command was sent (issued) in a waiting state.

(See FIG. 4(b)) (1) The cache memory 18 cancels the registration of the same area in response to the buffer invalidation request command from the cache memory IA (■=1→0).

Note that while the cache memory IB is waiting for the issuance of the buffer invalidation request command,
New write, requests from B are not terminated.

■ Since the cache memory IA has finished issuing the buffer invalidation request command from its own memory, the cache memory IA
It accepts the write request from PU2A and returns a write completion response.

■ Since the buffer invalidation request command was issued from cache memory l^ to the same area as the buffer invalidation request command that was in the waiting state, the cache memory IB cancels the waiting state, and
The contents of the store buffer held in step (2) are attempted to be reflected in the shared memory 3 by a write command.

■ Since the target area of the write command on the system bus 4 has already been internally changed in the cache memory IA, -
Assert the time interrupt signal (intercept signal).

(2) The shared memory 3 responds to the write command in step (2) with a retry request.

(See FIG. 4(c)) ① Cache memo January A writes the duplicate entry to the shared memory 3 in step ② (V=1→0).

[Phase] The cache memory IB issues the write command for step ■, which was requested to be retried at step ■.
M=1→0).

Note that a write request from CP02B to cache memory IB becomes a normal write operation after the above series of operations (■ to @) are completed. That is, shared memory 3 to 1
The current cache memory is loaded into the cache memory, and only its contents are changed.

FIG. 5 shows how the state of the cache memory in FIG. 2 changes.

In the figure, ■ is an invalid state (V=0), U is a valid and unchanged state J11 (v=1 and M=0), and M is a valid and changed state J11! (V = 1 and M = 1), Bl is in the state of waiting for a buffer invalidation request command to be issued, ST is in the state of waiting to store to the shared memory, (1) is new registration due to read operation, (2) is not yet registered. Writing to the change area, (3)
Waits for the buffer invalidation request command to be issued, (4) issues the buffer invalidation request command, and (5) waits for the buffer invalidation request command to be issued.
(6) Clear for replacement, (7) Copy back for replacement, (8) Detection of buffer invalidation request command for the same area, (9) Wait for store , and (10) indicates store completion. Note that the transition (6) from state JliU to state ill and the transition (7) from state [M to state ■] are performed by a clearing operation based on a buffer invalidation request command from another cache memory.

According to the control method of this embodiment, the cache memory LA,
When write requests to the same internal area occur simultaneously in IB, each cache memory IA (IB)
After sending the buffer invalidation request command to the system bus,
Other cache memory 1 for the same area within a predetermined time
When it detects a buffer invalidation request command from B(IA), it functions to ignore the command. In other words, more generally speaking, when buffer invalidation request commands are sent consecutively to the same area in a cache memory consisting of multiple cache memories, the second and subsequent buffer invalidation request commands are ignored (cancelled). It has become so.

Therefore, it is possible to invalidate the same area in another cache memory and achieve consistency control with the shared memory without erasing the rewritten data. Furthermore, it is possible to improve system performance by taking advantage of the copy-back method (high-speed processing).

Although this embodiment has described a buffer invalidation control method between two cache memories, it is natural that the above control method can be similarly applied between three or more cache memories (copy-back method). It will be obvious to business owners.

〔Effect of the invention〕

As explained above, according to the present invention, when a write request occurs simultaneously to the same area of each of a plurality of copy-back type cache memories, data in the target area is not lost and the shared memory It is possible to implement bumper invalidation processing by maximizing the high speed that is an advantage of the copy-back method.

This contributes to improving system efficiency.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are diagrams showing the principle of the buffer invalidation control method according to the present invention, and FIG. 2 is a block diagram showing the configuration of a tightly coupled multiprocessor system in which the buffer invalidation control method according to the present invention is applied. , FIG. 3 is a circuit diagram showing the internal configuration of the cache memory in FIG. 2, FIGS. Figure 5 is a state transition diagram of the cache memory in Figure 2, Figures 6 (a) to (c) are diagrams for explaining the problems of the conventional cache memory control method, and Figure 7 is the state transition diagram of the cache memory in Figure 6. 2 is a diagram showing the operation timing of the cache memory. FIG. (Explanation of symbols) M1 to Mn...Copy-back cache memory, CM...Shared memory, A...Address section, D...Data section, ■...Validity instruction flag, M. ...Changed instruction flag, Pl...Means (processing) for sending the buffer invalidation request command, P2...Set the address area included in the buffer invalidation request command from another cache memory into its own memory. P3: Register means; P4: Means (processing) for comparing the address included in the buffer invalidation request command from another cache memory with the contents of the register means. Figure 2 State transition diagram of cache memory in 1ST
... Store waiting state Figure 6 shows 81 Figure 9 shows the operation timing of the cache memory

Claims (1)

[Claims] 1. Multiple copy-back cache memories (M
In a multiprocessor system in which _1 to Mn) and at least one shared memory (CM) are connected via a system bus, each cache memory (Mi) has an address part (A) and a data part in each internal entry. (D), a valid indication flag (V) which indicates whether the area indicated by the access address exists in its own cache memory, and a changed indication flag (M) which indicates whether the data has been rewritten or not. and when there is a data write request from the corresponding CPU, if the target area is registered in the cache memory and the changed instruction flag is off, the write address from the CPU is means (P1) for sending a buffer invalidation request command including at least a portion thereof to the system bus; and means (P1) for monitoring a command on the system bus, and determining that the command is a buffer invalidation request command from another cache memory. means (P2) for erasing the address area included in the command from within its own cache memory when the command is issued; register means (P3) for holding the address of the buffer invalidation request command sent by itself; means (P) for comparing the address included in the buffer invalidation request command and the contents of the register means;
4), and if a buffer invalidation request command is detected from another cache memory for the same area within a certain period of time after sending the buffer invalidation request command, the command is controlled to be ignored. A buffer invalidation control method characterized by: 2. Further comprising means for delaying the address of the buffer invalidation request command held in the register means for a predetermined period of time, the delayed address being used as an address included in the buffer invalidation request command from the other cache memory. 2. The buffer invalidation control method according to claim 1, wherein the buffer invalidation control method is compared with the buffer invalidation control method.