JPH0498339A - Buffer invalidation control system - Google Patents

Abstract

PURPOSE:To make the maximum use of high speed so as to improve the performance of a whole system by canceling the transmission waiting state of a buffer invalidation request command and storing the content of a register means in a common memory. CONSTITUTION:When write requests are generated for the same areas of two cache memories (M1 and M2) and the writing of data in the cache memory (M1) is faster than that of the cache memory (M2), the buffer invalidation request command from the cache memory M1 is transmitted on a system bus and the cache memory M2 cancels the holding buffer invalidation request command and stores data stored in the register means P0 in the common memory(CM)3. When the issuing of the buffer invalidation request command from the self memory is terminated, a cache memory 1A receives the write request from corresponding CPU and returns the termination response. Thus, high speed being the merit of a copy back system is made the maximum use of and the efficiency of the system can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a technology for controlling buffer invalidation processing between multiple copy-back type cache memories, the present invention provides advantages of the copy-back type without erasing data rewritten in the cache memory. In order to take full advantage of the high speed of has and corresponds to CP
A register means for storing data and an address according to a write request from U, and when there is a data write request from the corresponding CPU, the target area is registered in the cache memory and the changed indication flag is set. When off, the write data according to the write request is stored in the target entry and the register means, the changed instruction flag is turned on, and a buffer invalidation request command containing at least a part of the write address is sent to the system. and a means for monitoring a command on the system bus and comparing an address included in the command with the write address, and in a state of waiting for sending of the buffer invalidation request command. If the command on the system bus is a buffer invalidation request command from another cache memory and the included address indicates the same area, cancel the sending wait state of the buffer invalidation request command, and The contents of the register means are configured to be stored in the shared memory in a store-through manner.

[Industrial application field]

The present invention relates to a multiprocessor system in which a plurality of copy/hack type cache memories and at least one shared memory are connected via a system bus,
In particular, the present invention relates to a technique for controlling buffer invalidation processing for invalidating the same area in other cache memories when write requests occur simultaneously to the same area in each cache memory.

[Conventional technology]

FIG. 6 shows an example of a conventional cache memory control mode.

In the illustrated example, both cache memories A and B are
It is assumed that this is a back-type cache memory. Further, ■ indicates a valid instruction flag indicating whether or not the area specified by the access address exists in the local cache memory, and M indicates a changed instruction flag indicating whether or not data has been rewritten.

For cache memories A and B, when there is a data write request from the corresponding CPU, the target area is registered in its own memory (V = 1) and the changed instruction flag M is set. When CM=0), the write data is written to the target area (entry), and the changed instruction flag M is turned on (M=1). When cache memory A (or B) writes data to an unmodified area, it sends a buffer invalidation request command BICMD to the system bus (write-once operation), thereby writing data to the same area in another cache memory B (or A). Clear (invalidate).

In the conventional system, once the write-once operation of both cache memories A and B started, they did not return a CPU write end response until the issuance of the buffer invalidation request command was completed.

Additionally, if the external access address matches the address of an internal modified entry, the cache memory sends an intercept signal to the cache memory that performed the external access, requesting that the access be temporarily suspended. , swap out (copy/
back).

Additionally, if an intercept signal is received from the outside while a write-once operation is being executed, the cache memory will
After the access of the device (other cache memory) that outputs the intercept signal is completed, the write-once (sending of the buffer invalidation request command) is executed again.

Note that FIG. 7 shows the state transition of the cache memory in FIG. 6.

In the figure, ■ is an invalid state (V=0), U is a valid and unmodified state 11 (V-1 and M=0), and M is a valid and modified state (
■ = 1 and M = 1), (1) is new registration by read operation, (2) is writing to an unchanged area and issuing a buffer invalidation request command, (3) is copying for replacement.・Back, (4) clear for replacement, and (5) write
Indicates new registration by action. Note that the transition (4) from state U to state I and the transition (3) from state M to state I are performed by a clearing operation based on a buffer invalidation request command from another cache memory.

[Problem to be solved by the invention]

In the conventional control method described above, when a response is not returned to the CPU until the write-once operation is completed without interruption, the advantages of the copy-hack method (reducing the frequency of bus access and high-speed processing) Therefore, the problem arises that the performance of the entire system deteriorates.

Furthermore, the method of swapping out one memory has the disadvantage that communication between the cache memory and the shared memory takes time.

In addition, in the method of executing write-once again, in the above example where write-once is required for both cache memories, write-once and intercept operations may be repeated for each other, possibly resulting in an infinite loop. Therefore, there is a problem that high-speed processing cannot be achieved.

Furthermore, a plurality of cache memories (in the example shown in FIG. 6, two
When data writes occur at the same time in two cache memories, if the timings perfectly match, a buffer invalidation request command is sent from both sides onto the system bus, and the data written in both cache memories is thereby lost. There is an inconvenience.

In order to avoid this inconvenience, countermeasures can be considered, such as allowing only one CPU to rewrite the shared area through software control (copy-on-write method), but this is extremely complicated to control. , cannot be called practical.

The present invention was created in view of the problems in the conventional technology, and it takes full advantage of the high speed that is the advantage of the copy-back method without erasing the data rewritten in the cache memory, thereby improving the efficiency of the entire system. The purpose of this invention is to provide a buffer invalidation control method that can contribute to improved performance.

[Means to solve the problem]

As shown in the principle diagrams in Figures 1(a) and (b),
The buffer invalidation control method of the present invention is applicable to a multiprocessor system in which a plurality of copy-back type cache memories old to Mn and at least one shared memory CM are connected via a system bus. In each internal entry, a valid indication flag V indicating whether the area indicated by the address section A1 data section D1 access address exists in its own cache memory, and a change indicating whether the data has been rewritten or not. A register means PO which has a completed instruction flag M and stores data and addresses according to a write request from the corresponding CPUC1, and a corresponding CPUC.
When there is a data write request from U, if the target area is registered in the cache memory and the changed instruction flag is off, the data written by the write request is sent to the target entry and the register means. and turn on the changed instruction flag,
means PI for sending a buffer invalidation request command including at least a part of the write address to the system bus; and means P2 for monitoring commands on the system bus and comparing the address included in the command with the write address. and when the command on the monitored system bus is a buffer invalidation request command from another cache memory while waiting for transmission of the buffer invalidation request command, and the included address points to the same area. In this case, the buffer invalidation request command is canceled and the content of the register means is stored in the shared memory in a store-through manner (P3).

[Effect]

To simplify the explanation, for example, two cache memories (
Assume that write requests occur simultaneously to the same area in the cache memory (M+9Mz), and data is written faster in one cache memory (M+) than in the other cache memory (M2).

In this case, a buffer invalidation request command from the cache memory is sent onto the system bus, and the cache memory A2 cancels the buffer invalidation request command that is pending (waiting to be sent) and stores it in the register means. The written data is stored in the shared memory CM (preventing loss of written data).

On the other hand, when the cache memory IA finishes issuing the buffer invalidation request command from its own memory, the cache memory IA
It can accept a write request from U and return a completion response. Also, since the sending of the buffer invalidation request command from the cache memory IB was canceled,
In the cache memory IA, data in the target area will not be lost.

In this way, when a write request to the same internal area occurs in multiple cache memories at the same time, when each cache memory is able to issue a buffer invalidation request command, it performs its own write-rinse operation. After completion, it is possible to update the corresponding internal entry and return a write completion response to the CPU, and on the other hand, when a buffer invalidation request command is received, the contents of the register means can be reflected in the shared memory in a store-through manner. I can do it. This allows you to avoid losing rewritten data.
It becomes possible to invalidate the same area in another cache memory, and furthermore, to take full advantage of the high speed that is an advantage of the copy-back method, contributing to improving system efficiency.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 2 shows the configuration of a tightly coupled multiprocessor system to which the buffer invalidation control method of the present invention is applied.

In this system, a plurality of copy-back type cache memories IA and IB (in this embodiment, only two are shown for simplicity of illustration) are connected to at least one cache memory via a system bus 4.
shared memory 3 (also only one is shown for simplicity)
It is connected to the. In addition, each cache memory IA, I
B is a central processing bag that supplies address information to the corresponding cache memory and controls data reading and writing. (CPU) 2A and 2B are connected.

FIGS. 3(a) and 3(b) show the internal structure of the cache memory in FIG. 2.

In FIG. 3(a), 31 is a tag part (tag memo), which includes an address part that stores the physical address of the access data, and whether or not the area specified by the access address exists in the local cache memory. It has a valid indication flag ■ which indicates that the data has been rewritten, and a changed indication flag M which indicates whether or not the data has been rewritten.
indicates "on" or "1" when each condition is affirmed, and "off" or "0" when each condition is denied.
exhibits.

32 is a decoder (DEC) that decodes the address ADDI from the corresponding CPU; 33 is a comparison circuit that responds to the address registered in the tag section 31, the address ADDI from the CPU, and the flag V bit; 34 is a decoder (DEC) that decodes the address ADDI from the CPU; An inverter 35 responds to the read/write control signal R/-, an inverter 36 responds to the flag M bit.
is the output of the comparison circuit 33 and the output of the inverter 34 (CPU
an AND gate that sets the bit of flag M (signal MSET) in response to write signal CWRT);
37 is the output of the comparison circuit 33 and the output CW of the inverter 34
an AND gate responsive to RT and the output of inverter 35;
38 is a store buffer that stores the address ADDI from the corresponding CPU, and 39 is a buffer invalidation control circuit that outputs the invalidation address IAD supplied from the store buffer 38, the output -U of the AND gate 37, and the cancel signal CNL. (described later), it has a function of creating a buffer invalidation request command, sending it to the system bus 4, canceling the sending of the command, and outputting a signal CIEND instructing the end of issuing the command.

Similarly, 40 is a decoder (DEC) that decodes the address ADD2 on the system bus 4, and 41 is the address registered in the tag unit 31 and the address AD on the system bus 4.
Comparison circuit responsive to bit D2 and flag ■; 42 is invalidation address IAD supplied from store buffer 38;
(3Q bit) and address ADD2 on system bus 4
(In this case, the comparison circuit responds to the address BIAD of the buffer invalidation request command from another cache memory), and 43 is the write data D from the corresponding CPU.
44 is a store operation control circuit which stores the store address SA (32 bits) supplied from the store buffer 38, the store data SD supplied from the store buffer 43, and the output from the comparison circuit 42. In response to a store command activation signal SC5 (described later), a signal 5 instructs to create a store command, send it to the system bus 4, and terminate the store operation.
It has a function to output END.

Note that in the comparison circuit 33, the valid instruction flag ■ is on (V=
In the state of 1), the address of the tag section 31 and the CPU address A
When DDI matches, the output is set to "do", thereby making the corresponding AND gate 36 "enabled". In this state (the output of the comparison circuit 33 is "l"), the changed instruction flag M is turned off (M= 0), the output of the inverter 35 becomes "Bi" and the AND gate 37 becomes "valid". On the other hand, the comparison circuit 41 detects that the valid instruction flag V is on (V=1
), when the address of the tag section 31 and the address ADD2 on the system bus 4 match, the bit of the flag (2) is cleared (signal VCLR). Further, when the address BIAD of the buffer invalidation request command from another cache memory on the system bus 4 and the invalidation address IAD from the store buffer 38 match, the comparison circuit 42 sends a message to the buffer invalidation control circuit 39. In addition to supplying the cancel signal CNL, the store operation control circuit 44
The above store command activation signal SC8 is supplied to.

The circuit shown in FIG. 3(b) includes an OR game (OR game) 51 that responds to a buffer invalidation request command issuance end instruction signal CIEND and a store operation end instruction signal 5END, and a CPU.
A J-type flip-flop 52 receives the write signal CWRT, the output of the OR gate 51, and the external clock φ at the J terminal, K terminal, and clock terminal CLK, respectively, and outputs the store buffer busy signal SBB to the Q output terminal.
, a comparison circuit 53 that detects the match/mismatch between the invalidation address IAD from the store buffer 38 and the address ADDI from the CPU, an AND gate 54 that responds to the output of the comparison circuit and the CPU write signal CWRT, and the AND gate. and an AND gate 55 responsive to the output of the AND gate 37 (see FIG. 3(a)) and the store buffer busy signal SBB; CPU wait signal C in response to the outputs of gates 55 and 56
and an OR gate 56 that generates WT.

Next, a buffer invalidation control method will be explained with reference to FIGS. 4(a) and 4(b).

(See Figure 4 (a)) ■ Cache memories IA and IB are used for areas registered in their own memory (V = 1) and where the changed instruction flag is off (M = 0). Corresponding C P
When there is a write request from U2A or 2B, the data and address from the write request are held in the target entry and the store buffer 43.38, and a corresponding CPU write completion response is returned. At this time, the rewrite target entry remains unchanged. In order to transition from the state to the changed state, each of the cash memos January A and 1B turns on the changed indication flag M (M=1).

■ Cache memory IA sends a buffer invalidation request command to system bus 4 (write-once operation)
.

■ Cache memory IB sends (issues) a buffer invalidation request command in the same way as cache memory IA.
However, because the cache memory IA happened to operate faster, the right to use the system bus could not be acquired, and the buffer invalidation request command was sent (issued) in a waiting state.

(See FIG. 4(b)) ① The cache memory IB cancels the registration of the same area in response to the buffer invalidation request command from the cache memory IA.

In addition, in the cache memo January B, when the buffer invalidation request command is being issued, the CPU 2 for the same area is
A new write request from B is not terminated.

- Since the cache memory IJIA has finished issuing the buffer invalidation request command from its own memory, it accepts the write request from the corresponding CPU 2A and returns a write completion response.

■ Cache memo January B has issued a buffer invalidation request command from the cache memory IA to the same area as the buffer invalidation request command that was in the issuance waiting state, so it cancels the issuance waiting state and
The contents of the store buffer held in step (2) are stored in the shared memory 3 in a store-through manner by a write command (V=1→0). This can prevent write data from disappearing.

FIG. 5 shows how the state of the cache memory in FIG. 2 changes.

In the figure, I, U, M, (1), (3), (4), and (5) are the same as those in FIG. 7, so their explanation will be omitted. ST is waiting to store to shared memory,
Bl indicates a state of waiting for the issuance of a buffer invalidation request command. Also, (2a) writes to the unmodified area, (2b
) is issuing a buffer invalidation request command, (6) is waiting for a buffer invalidating request command to be issued, (7) is detecting a buffer invalidating request command for the same area, (8) is waiting for a store, and (9) is waiting for a buffer invalidating request command to be issued. Indicates store completion.

As explained above, according to the control method of this embodiment, when write requests to the same internal area occur simultaneously in cache memories IA and IB, one cache memory LA (IB) responds to the buffer invalidation request. It is possible to issue a command, rewrite the corresponding entry after the write-rinse operation is completed, and return a CPU write completion response. In contrast, the other cache memory IB (
1^) cancels the state in which it is waiting to send a buffer invalidation request command in its own memory, and upon receiving the buffer invalidation request command from another cache memo A (IB), writes the contents of the store buffer 38.43. Write to the shared memory 3 using one method of store and through.

This makes it possible to invalidate the same area in other cache memories without losing rewritten data, and also to improve system performance by taking advantage of the copy-back method (high-speed processing). becomes possible.

Although this embodiment has described a buffer invalidation control method between two cache memories, it is natural that the above control method can be similarly applied between three or more cache memories (copy-back method). It will be obvious to business owners.

〔Effect of the invention〕

As explained above, according to the present invention, when write requests are made simultaneously to the same area of each of a plurality of copy-back type cache memories, data rewritten in the cache memory is not lost. Buffer invalidation processing can be realized by taking full advantage of the high speed that is an advantage of the copy-back method, thereby making it possible to improve the performance of the entire system.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are principle diagrams of the buffer invalidation control method according to the present invention, and FIG. 2 is a block diagram showing the configuration of a tightly coupled multiprocessor system to which the buffer invalidation control method of the present invention is applied. , Figures 3(a) and (b) are circuit diagrams showing the internal configuration of the cache memory in Figure 2, and Figures 4(a) and (b) are chronological diagrams of the cache memory control form in the system in Figure 2 5 is a state transition diagram of the cache memory in FIG. 2, FIG. 6 is a diagram for explaining the problems of the conventional cache memory control method, and FIG. 7 is a state transition diagram of the cache memory in FIG. 6. This is a memory state transition diagram. (Explanation of symbols) A, ~Mn...Copy-back cache memory, C...Shared memory, A...Address section, D...Data section, ■...Validity instruction flag, M ...changed instruction flag, Ci...corresponding CPU, po...register means, Pl...means for storing data in the target entry and register means and sending out a J buffer invalidation request command (
P2...Means for comparing the address of the command on the system bus and the write address (processing), P3...Cancels the sending waiting state of the buffer invalidation request command, and stores the contents of the register means in the shared memory. Process to store. Figure 2 Figure 47 Figure 2 (Cache memory state transition diagram [...Invalid state U...Valid and unchanged state M...Valid and changed state BI...Buffer invalidation Request command issuance wait state ST: store wait state

Claims (1)

[Claims] 1. Multiple copy-back cache memories (M
In a multiprocessor system in which _1 to Mn) and at least one shared memory (CM) are connected via a system bus, each cache memory (Mi) has an address part (A) and a data part in each internal entry. (D), a valid indication flag (V) which indicates whether the area indicated by the access address exists in its own cache memory, and a changed indication flag (M) which indicates whether the data has been rewritten or not. and register means (P0) for storing data and addresses in response to a write request from the corresponding CPU (Ci), and when there is a data write request from the corresponding CPU, the target area is If it is registered in the cache memory and the changed instruction flag is off, the write data according to the write request is stored in the target entry and the register means, the changed instruction flag is turned on, and the write address is means (P1) for sending a buffer invalidation request command containing at least a part of the buffer invalidation request command to the system bus; and means (P2) for monitoring a command on the system bus and comparing the address included in the command with the write address. ), and in the buffer invalidation request command sending waiting state, the monitored command on the system bus is a buffer invalidation request command from another cache memory, and the contained address points to the same area. If the buffer invalidation request command has been sent, the buffer invalidation request command is canceled and the contents of the register means are stored.
A buffer invalidation control method characterized in that storage is performed in the shared memory in a through method (P3). 2. The buffer invalidation control method according to claim 1, wherein the cache memory opens the register means when sending of the buffer invalidation request command is completed. 3. The cache memory monitors a buffer invalidation request command from another cache memory on the system bus, and erases an address area included in the command from within its own cache memory. Buffer invalidation control method described in . 4. The buffer invalidation control method according to claim 1, wherein the cache memory returns a completion response to a write request from the corresponding CPU before sending the buffer invalidation request command. 5. The cache memory has means for comparing a part of the address in the register means with an address according to a new write request from the corresponding CPU, and the cache memory is configured to compare a part of the address in the register means with an address according to a new write request from the corresponding CPU, and according to a new write request to the area targeted for buffer invalidation. 3. The buffer invalidation control method according to claim 2, wherein an end response is not returned until the register means is in an open state. 6. In the cache memory, when there is a new write request from the corresponding CPU to an area where the valid instruction flag is on and the changed instruction flag is off, the register means is in an open state. 3. The buffer invalidation control method according to claim 2, wherein an end response is not returned to the write request until .